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confidential preliminary cynse10512 cynse10256 CYNSE10128 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-02069 rev. *f revised july 13, 2004 ayama? 10000 network search engine [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 2 of 153 table of contents 1.0 features .................................................................................................................. .................. 10 2.0 overview .................................................................................................................. .................. 11 3.0 device architecture over view .......................................... ................................ ............... 13 3.1 data array, mask array and table widths ................................................................................ 13 3.2 data and mask addressing .................................................................................................. ..... 14 3.3 successful search and multiple match arbitration .................................................................... 14 4.0 signals description ....................................................................................................... ....... 15 5.0 functional description .................................................................................................... ... 18 5.1 modes of operation ........................................................................................................ .......... 18 5.1.1 non-enhanced mode ....................................................................................................... ............... 18 5.1.2 enhanced mode ........................................................................................................... ................... 18 5.1.2.1 mini-key .............................................................................................................. .......................................... 19 5.1.2.2 soft priority ......................................................................................................... .......................................... 19 5.1.2.3 parity ................................................................................................................ ............................................. 20 5.1.2.4 multisearch ........................................................................................................... ........................................ 22 5.1.2.5 enhanced learn operation .............................................................................................. ............................ 23 5.2 i/o interfaces ............................................................................................................ ................ 23 5.2.1 asic interface .......................................................................................................... ....................... 24 5.2.2 sram interface .......................................................................................................... ..................... 24 5.2.3 cascade interface ....................................................................................................... .................... 24 5.3 output signals default driver/last device designation (lram and ldev) ............................. 25 5.4 registers ................................................................................................................. .................. 25 5.4.1 comparand register (cmpr) ............................................................................................... .......... 26 5.4.2 global mask register (gmr) .............................................................................................. ............ 26 5.4.3 search successful register (ssr) ........................................................................................ ......... 27 5.4.4 command register (command) .............................................................................................. ..... 28 5.4.5 information register (info) ............................................................................................. ............... 30 5.4.6 read burst address register (rburreg) ................................................................................... .30 5.4.7 write burst address register (wburreg) .................................................................................. .. 31 5.4.8 next-free address register (nfa) ........................................................................................ .......... 31 5.4.9 configuration register (config) ......................................................................................... .......... 32 5.4.10 hardware register (hardw are) ........................................................................................... ..... 33 5.4.11 parity control register (parity) ....................................................................................... ........... 34 5.4.12 control register (cpr[0:15]) ........................................................................................... ............. 35 5.4.13 search result register (srr[15:0]) ..................................................................................... ........ 36 5.4.14 block mini-key register (bmr) .......................................................................................... ........... 37 5.4.15 block priority register (bpr) .......................................................................................... .............. 38 5.4.16 block parity register (bpar) ............... ................ ................. ................ ................ ........... ............. 39 5.4.17 block nfa register (bnfa) .............................................................................................. ............ 39 5.4.18 block priority register aliases (bpra) ................................................................................. ........ 40 5.5 multi-hit description ..................................................................................................... ............. 41 5.6 clocks .................................................................................................................... ................... 42 5.7 phase-locked loop ......................................................................................................... ......... 43 5.8 pipeline latency .......................................................................................................... .............. 43 5.9 dq bus encoding of ayama 10000 address space ................................................................. 43 5.9.1 addressing the data array, mask array and external sram .... ..................................................... 44 5.9.2 addressing the internal registers ....................................................................................... ............ 45 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 3 of 153 table of contents (continued) 5.10 depth cascading .......................................................................................................... .......... 45 5.10.1 depth cascading up to eigh t devices in one block ..................................................................... 45 5.10.2 depth cascading up to 31 devices in 4 blo cks ........................................................................... .47 5.10.3 depth cascading for a full signal ........ .............................................................................. ........ 47 5.11 device selection in a cascaded system ................................................................................ 48 5.12 power-up sequence ........................................................................................................ ....... 49 6.0 operations and timing di agrams ...................................... ................................ ............... 50 6.1 command encoding .......................................................................................................... ....... 50 6.2 command bus parameters .................................................................................................... ... 50 6.2.1 non-enhanced mode (emode = 0) ........................................................................................... .... 50 6.2.2 enhanced mode (emode = 1) with multisearch disabled (mse = 0) ............................................ 51 6.2.3 enhanced mode (emode = 1) with multisearch enabled (mse = 1) ............................................ 51 6.3 read command .............................................................................................................. .......... 51 6.3.1 single read ...................................... ....................................................................... ........................ 52 6.3.2 burst read .............................................................................................................. ........................ 52 6.3.3 read parity ............................................................................................................. ........................ 53 6.4 write command ............................................................................................................. ........... 53 6.4.1 single write ............................................................................................................ ......................... 54 6.4.2 burst write ............................................................................................................. ......................... 54 6.4.3 parallel write .......................................................................................................... ......................... 55 6.5 search command ............................................................................................................ ......... 56 6.5.1 mixed-size single searches with one device on tables configured with different widths ........... 56 6.5.2 mixed-size multi searches with one device on tables configured with different widths .............. 58 6.5.3 72-bit single se arch for 1 device or cascade up to eight devices ................................................... 60 6.5.4 72-bit multisearch for one de vice or cascade up to eight devi ces .............................................. 65 6.5.5 144-bit single search for ca scade up to 31 devices ................ ..................................................... 7 2 6.5.6 576-bit single search for one device or cascad e up to eight devices ......................................... 85 6.5.7 576-bit multisearch for one de vice or cascade up to eight devices ............................................. 89 6.5.8 mixed-size single searches with 31 devices on tables configured with different widths ............ 95 6.5.9 mixed-size multi searches wit h 8 devices on tables configured with different widths ............... 107 6.6 learn command ............................................................................................................. ........ 113 6.6.1 non-enhanced mode ....................................................................................................... ............. 113 6.6.2 enhanced mode ........................................................................................................... ................. 114 6.6.3 learn operation on depth-ca scaded table ................................................................................. 117 6.7 sram pio access ........................................................................................................... ....... 121 6.7.1 sram read with a table of one device .................................................................................... .. 121 6.7.2 sram read with a table of up to eight devi ces .......................................................................... 1 22 6.7.3 sram read with a table of up to 31 devices .............................................................................. 125 6.7.4 sram write with a table of one device ...... ............................................................................. ... 127 6.7.5 sram write with a table of up to eight devi ces .......................................................................... 129 6.7.6 sram write with table(s) consisting of up to 31 devices ........................................................... 131 6.8 timing sequences for back-to-back operations .................................................................... 133 6.9 full signal timing diagram ................................................................................................ ..... 134 7.0 jtag (ieee 1149.1) ........................................................................................................ ............. 135 8.0 power consumption ......................................................................................................... ... 136 9.0 electrical specificatio ns .............................. .......................................... ........................ 1 37 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 4 of 153 table of contents (continued) 10.0 ac timing parameters, waveforms and test conditions ................................... 138 10.1 ac timing parameters and waveforms with clk2x ........................................................... 138 10.2 ac timing parameters and waveforms with clk1x ........................................................... 140 10.3 ac test conditions and output loads ................................................................................. 143 10.3.1 lvcmos 2.5v/1.8v ....... ................................................................................................ ............. 143 10.3.2 hstl i/ii .............................................................................................................. ........................ 144 11.0 pin assignment and pinout diagram ........................................................................... 145 12.0 package diagrams ......................................................................................................... .... 151 13.0 ordering information ..................................................................................................... . 151 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 5 of 153 list of figures figure 2-1. ayama? 10000 block diagram ......................................................................................... .11 figure 2-2. example of switch/router implementation using ayama 10000 ........................................ 12 figure 3-1. ayama 10000 database table widths ................................................................................ 13 figure 3-2. multi-width database configuration example..................................................................... 13 figure 3-3. addressing the ayama 10000 data and mask arrays......................................................... 14 figure 5-1. blocks and block registers association ............................................................................. 19 figure 5-2. mini-key register contents......................................................................................... ........ 19 figure 5-3. sub-blocks and soft priority associations .......................................................................... 20 figure 5-4. timing diagram of a dq bus parity error (288-bit search, tlsz=00)................................ 21 figure 5-5. timing diagram of a core parity error (tlsz=00).............................................................. 22 figure 5-6. multisearch operation overview..................................................................................... .... 22 figure 5-7. ayama 10000 i/o interfaces......................................................................................... ....... 24 figure 5-8. comparand register selection during search and learn instructions ............................... 26 figure 5-9. addressing the global mask register array ....................................................................... 27 figure 5-10. search successful register ........................................................................................ ...... 27 figure 5-11. command register .................................................................................................. ......... 28 figure 5-12. information register .............................................................................................. ............ 30 figure 5-13. read burst register ............................................................................................... ........... 30 figure 5-14. write burst addres s register ...................................................................................... ...... 31 figure 5-15. next-free address register ........................................................................................ ....... 31 figure 5-16. configuration r egister............................................................................................ ........... 32 figure 5-17. hardware register ................................................................................................. ........... 33 figure 5-18. parity control register ........................................................................................... ........... 34 figure 5-19. selection of the cpr through gmr index......................................................................... 35 figure 5-20. control register .................................................................................................. .............. 35 figure 5-21. search result register ............................................................................................ ......... 36 figure 5-22. block mini-key register ........................................................................................... ......... 37 figure 5-23. block priority register ........................................................................................... ............ 38 figure 5-24. block parity register ............................................................................................. ............ 39 figure 5-25. block nfa register ................................................................................................ ........... 39 figure 5-26. block priority register aliases ................................................................................... ....... 40 figure 5-27. ayama 10000 clocks (clk2x and phs_l) ...................................................................... 42 figure 5-28. ayama 10000 clocks (clk1x)........................................................................................ .. 42 figure 5-29. ayama 10000 clocks for all timing diagrams .................................................................. 42 figure 5-30. data array, mask array and exte rnal sram address s pace encoding ........................... 44 figure 5-31. internal register address space encoding....................................................................... 45 figure 5-32. depth cascading in a single block ................................................................................. .. 46 figure 5-33. depth cascading 4 blocks .......................................................................................... ...... 47 figure 5-34. full signal generation in a cascaded table.................................................................. 48 figure 5-35. proper power-up sequence .......................................................................................... .... 49 figure 6-1. single-location read cycle timing .................................................................................. .. 52 figure 6-2. burst read of the data and mask arrays (blen = 4) ......................................................... 53 figure 6-3. single write cycle timing .......................................................................................... ......... 54 figure 6-4. burst write of the data and mask arrays (blen = 4) ......................................................... 55 figure 6-5. timing diagram for mixed single search (one device)...................................................... 57 figure 6-6. multiwidth conf igurations using cynse10512 as an example .......................................... 58 figure 6-7. timing diagram for mixed multisearch (one device) ......................................................... 59 figure 6-8. multiwidth conf igurations using cynse10512 as an example .......................................... 60 figure 6-9. hardware diagram for a tabl e with eight devices.............................................................. 61 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 6 of 153 list of figures (continued) figure 6-10. timing diagram for 72-bit search device number 0......................................................... 62 figure 6-11. timing diagram for 72-bit search device number 1......................................................... 63 figure 6-12. timing diagram for 72-bit search device number 7 (last device) .................................. 64 figure 6-13. 72 table with eight devices ............................................................................................ 65 figure 6-14. hardware diagram for a table with eight devices for multisearch .................................. 66 figure 6-15. timing diagram for 72-bit multisearch device number 0 ................................................. 68 figure 6-16. timing diagram for 72-bit multisearch device number 1 ................................................. 69 figure 6-17. timing diagram for 72-bit multisear ch device number 7 (last device) ........................... 70 figure 6-18. 72 table with in multisearchmode................................................................................... 71 figure 6-19. hardware diagram for a table with 31 devices ................................................................ 73 figure 6-20. 144-bit search for devices in bloc k #0 and above block #1 winning device .................. 74 figure 6-21. 144-bit search timing diagram fo r block #1 global winning device ............................... 75 figure 6-22. 144-bit search timing diagram for devices below block #1 winning device .................. 76 figure 6-23. 144-bit search timing diagram for devices above block #2 winning device.................. 77 figure 6-24. 144-bit search timing diagram fo r block #2 global winning device ............................... 78 figure 6-25. 144-bit search timing diagram for devices below block #2 winning device .................. 79 figure 6-26. 144-bit search timing diagram for devices above block #3 winning device.................. 80 figure 6-27. 144-bit search timing diagram fo r block #3 global winning device ............................... 81 figure 6-28. 144-bit search diagram below block #3 winning device except the last device ........... 82 figure 6-29. 144-bit search timing diagram for device number 6 in block #3 .................................... 83 figure 6-30. 144 table with 31 devices .............................................................................................. 84 figure 6-31. timing diagram for 576-bit single search device number 0............................................ 86 figure 6-32. timing diagram for 576-bit single search device number 1............................................ 87 figure 6-33. timing diagram for 576-bit single s earch device number 7 (last device) ..................... 88 figure 6-34. 576 table with eight devices .......................................................................................... 89 figure 6-35. timing diagram for 576-bit multisearch device number 0 ............................................... 91 figure 6-36. timing diagram for 576-bit multisearch device number 1 ............................................... 92 figure 6-37. timing diagram for 576-bit multisearch device number 7 (last device) ......................... 93 figure 6-38. 576 table with eight devices .......................................................................................... 94 figure 6-39. multiwidth configurations example with cynse10512s................................................... 95 figure 6-40. timing diagram for mixed search for devices above block 0 winning device ................ 96 figure 6-41. timing diagram for mixed sear ch for block 0 winning device ......................................... 97 figure 6-42. timing diagram for mixed search for devices below block 0 winning device ................ 98 figure 6-43. timing diagram for mixed search above block 1 winning device ................................... 99 figure 6-44. timing diagram for mixed sear ch for block 1 winning device ....................................... 100 figure 6-45. timing diagram for mixed sear ch below block 1 winning device ................................. 101 figure 6-46. timing diagram for mixed search above block 2 winning device ................................. 102 figure 6-47. timing diagram for mixed sear ch for block 2 winning device ....................................... 103 figure 6-48. timing diagram for mixed sear ch below block 2 winning device ................................. 104 figure 6-49. timing diagram for mixed search for a ll except the last device in block 3 .................. 105 figure 6-50. timing diagram for mixed search for the last device in block 3 ................................... 106 figure 6-51. multiwidth configurations exampl e for multisearch with cynse10512s ....................... 107 figure 6-52. timing diagram for mixed multisearch (eight devices) for device 0.............................. 109 figure 6-53. timing diagram for mixed multisearch (eight devices) for device 1.............................. 110 figure 6-54. timing diagram for mixed multisearch (eight devices) for device 2.............................. 111 figure 6-55. timing diagram for mixed multisearch (eight devices) for device 7.............................. 112 figure 6-56. timing diagram of 72-bit learn from dq bus and cmpr registers (one device) ........ 114 figure 6-57. timing diagram of 288-bit learn from dq bus and cmpr registers (one device) ...... 115 figure 6-58. timing diagram of 576-bit learn from dq bus (one device) ......................................... 116 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 7 of 153 list of figures (continued) figure 6-59. timing diagram of 576-bit learn fr om cmpr register (one device) ............................ 117 figure 6-60. timing diagram of learn (tlsz = 00 (binary) , ldev = 1 (binary)) ................................... 118 figure 6-61. timing diagram of learn (except on the last device [tlsz = 01 (binary)])................... 119 figure 6-62. timing diagram of learn on device number 7 (tlsz = 01 (binary)).............................. 120 figure 6-63. sram read access (tlsz = 00 (binary), hlat = 000 (binary), lram = 1 (binary), ldev = 1 (binary)).......................................................................................... ...... 122 figure 6-64. hardware diagram of a bloc k of eight devices .............................................................. 123 figure 6-65. sram read of device #0 in a block of eight devices .................................................... 124 figure 6-66. sram read timing of device #7 in a block of eight devices ........................................ 125 figure 6-67. hardware diagram of 31 de vices using four blocks ..................................................... 126 figure 6-68. sram read of device #0 in a bank of 31 devices......................................................... 126 figure 6-69. sram read of device #0 in a bank of 31 devices......................................................... 127 figure 6-70. sram write access (tlsz = 00 (binary), hlat = 000 (binary), lram = 1 (binary), ldev = 1 (binary)).......................................................................................... ...... 128 figure 6-71. hardware diagram of a bloc k of eight devices .............................................................. 129 figure 6-72. sram write of device #0 in a block of eight devices .................................................... 130 figure 6-73. sram write timing of device #7 in block of eight devices ........................................... 131 figure 6-74. table of 31 devices (four blocks) ................................................................................. .132 figure 6-75. sram write of device #0 in bank of 31 devices ............................................................ 132 figure 6-76. sram write through device #30 in bank of 31 devices ............................................... 133 figure 6-77. timing diagram for full signal (tlsz = 10).................................................................... 134 figure 8-1. typical power consumption of ayama 10000 .................................................................. 136 figure 10-1. ac timing wave forms with clk2x .............................................................................. 139 figure 10-2. ac timing wave forms with clk1x .............................................................................. 142 figure 10-3. lvcmos i/o input waveform ......................................................................................... 143 figure 10-4. test condition of 2.5v lvcmos i/o output load equivalent ........................................ 143 figure 10-5. test condition of 2.5v high-z lvcmos i/o output load equivalent ........................... 143 figure 10-6. test condition of 1.8v high-z lv cmos i/o output load equivalent ............................ 143 figure 10-7. hstl i/ii i/o input waveform ...................................................................................... .... 144 figure 10-8. test condition of hstl i i/o output load equivalent..................................................... 144 figure 10-9. test condition of hstl ii i/o output load equivalent.................................................... 144 figure 10-10. test condition of hstli/ii i/o high-z output load equivalent..................................... 144 figure 11-1. pinout diagram (top view) ......................................................................................... .... 145 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 8 of 153 list of tables table 3-1. bit position match ................................................................................................. ............... 14 table 4-1. ayama? 10000 signal description .................................................................................... .15 table 5-1. summary of non-enhanced and enh anced mode features and functions differences .... 18 table 5-2. selection of search key, gmr, and cmpr in multisearch operation ................................ 23 table 5-3. list of internal registers ......................................................................................... ............. 25 table 5-4. search successful register description ............................................................................. 28 table 5-5. command register description ....................................................................................... .... 28 table 5-6. information register description ................................................................................... ...... 30 table 5-7. read burst register description .................................................................................... ..... 30 table 5-8. write burst register description ................................................................................... ...... 31 table 5-9. nfa register description ........................................................................................... ......... 31 table 5-10. configuration register description ................................................................................ .... 32 table 5-11. hardware register description ..................................................................................... ..... 33 table 5-12. parity control register description ............................................................................... .... 34 table 5-13. control register .................................................................................................. ............... 35 table 5-14. search result register ............................................................................................ .......... 36 table 5-15. srr?s index composition based on status ................................................................ 36 table 5-16. block mini-key register description ............................................................................... .. 37 table 5-17. block priority register description ............................................................................... ..... 38 table 5-18. block parity register description ................................................................................. ..... 39 table 5-19. block nfa register description .................................................................................... .... 39 table 5-20. block priority register alias for priority #0 fields ............................................................. 4 1 table 5-21. block priority register alias for priority #1 fields ............................................................. 4 1 table 5-22. block priority register alias for priority #2 fields ............................................................. 4 1 table 5-23. block priority register alias for priority #3 fields ............................................................. 4 1 table 5-24. pipeline stages and maximum operating speed. ............................................................. 43 table 5-25. data array, mask array and exte rnal sram address space encoding ........................... 44 table 5-26. sram address generation ........................................................................................... .... 44 table 5-27. internal register address space encoding ....................................................................... 45 table 5-28. cascadability of operations and features ........................................................................ 45 table 6-1. command codes ...................................................................................................... ........... 50 table 6-2. single/burst read command parameters .......................................................................... 51 table 6-3. single/burst write command parameters ........................................................................... 54 table 6-4. tlsz[1:0] description .............................................................................................. ............ 56 table 6-5. shift of ssf and ssv from sadr ..................................................................................... .. 58 table 6-6. hit/miss assumptions ............................................................................................... ........... 61 table 6-7. hit/miss assumption for multisearch mode ......................................................................... 67 table 6-8. hit/miss assumptions ............................................................................................... ........... 72 table 6-9. hit/miss assumptions ............................................................................................... ........... 85 table 6-10. hit/miss assumptions for 576-bit multi search .................................................................. 90 table 6-11. hit/miss assumptions .............................................................................................. .......... 95 table 6-12. hit/miss assumptions in multisearchmode ..................................................................... 108 table 6-13. sram write cycle latency from second cycle of learn instruction .............................. 120 table 6-14. required idle cycles between commands ..................................................................... 133 table 7-1. supported operations ............................................................................................... ........ 135 table 7-2. tap device id register ............................................................................................. ........ 135 table 9-1. dc electrical characteristics for ayama 10000 ................................................................. 137 table 9-2. operating conditions for ayama 10000 ............................................................................ 137 table 10-1. ac timing parameters with clk2x ................................................................................ 138 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 9 of 153 list of tables (continued) table 10-2. ac timing parameters with clk1x ................................................................................ 140 table 10-3. jtag timing parameters ............................................................................................ .... 141 table 10-4. 2.5v / 1.8v ac table for lvcmos test condition of ayama 10000 .............................. 143 table 10-5. 1.5v ac table for hstl test condition of ayama 10000 .............................................. 144 table 11-1. pin assignment .................................................................................................... ............ 146 table 13-1. ordering information .............................................................................................. .......... 151 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 10 of 153 1.0 features ? up to 512k 36-bit entries in a single device for cynse10512 ? 256k entries in 72-bit configuration ? 128k entries in 144-bit configuration ? 64k entries in 288-bit configuration ? 32k entries in 576-bit configuration ?up to 256k 36-bit entries in a single device for cynse10256 ? 128k entries in 72-bit configuration ? 64k entries in 144-bit configuration ? 32k entries in 288-bit configuration ? 16k entries in 576-bit configuration ?up to 128k 36-bit entries in a single device for CYNSE10128 ? 64k entries in 72-bit configuration ? 32k entries in 144-bit configuration ? 16k entries in 288-bit configuration ? 8k entries in 576-bit configuration ? multiple width tables in a single device ? single-cycle search operat ion on 72-/144-bit tables ? mini-key ? -programmable search key for fine grain table selection and power conservation ? prioritized blocks with no overhead in table management using programmable soft priority ? ? parity support for reliable operation ? non-enhanced mode and enhanced mode operation ? up to 133 million searches per second in 72-/144-bit configuration ? up to 66.5 million searches per second in 36-/288-bit configuration ? up to 33.25 million searches per second in 576-bit configuration (enhanced mode only) ? enhanced mode with multisearch ? operation ? up to 266 million searches per second in 72-/144-bit configuration ? up to 133 million searches per second in 36-/288-bit configuration ? up to 66.5 million searches per second in 576-bit configuration ? cascadable for depth expansion ? glueless interface to industry-standard srams and ssrams ? simple hardware instruction interface ? ieee 1149.1 test access port ? 1.2v core voltage supply ? supports 1.5v hstl and 1.8v/2.5v lvcmos i/o standards ? 388-pin bga package [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 11 of 153 2.0 overview cypress semiconductor corporation?s (cypress?s) ayama? 10000 network search engine (nse) is designed to be a high- performance, pipelined, synchronous, 512k/2 56k/128k 36-bit entries nse. this hi gh-speed, high-capacity ayama 10000 nse can be deployed in a variety of networking and communications appl ications. it can be used to accelerate network protocols such as longest-prefix match (cidr), arp, mpls, and other layer 2, 3, and 4 protocols. the performance and features of the ayama 10000 make it attractive in applications such as ente rprise lan switches and router s, and broadband switching and/or routing equipment that suppor ts multiple data rates at oc?48 and beyond. ayama 10000 can operate at a maximum performance of 266 million searches per second (msps). the ayama 10000 is designed to be scalable in order to support network database sizes of up to 15872k 36-bit entries specifical ly for environments that require large network policy databases. it includes features that ease table management, reduce power consumption and improve data integrity. the device can have it s features individually enabled or disabled for flexibility based on the needs of the applications. the ayama 10000?s data and mask a rrays that make up the core are organized into blocks that can be individually configured to optimize the de vice performance and provide even more flexibility. figure 2-1 below shows the block diagram of the ayama 10000. compare / pio data address decode match logic dq[71:0] cmdv cmd[10:0] lhi[6:0]/lhi_0[6:0] command pio access priority encode cmd arbitration logic lho[1:0]/lho_0[1:0] and sram interface sadr[n:0], oe_l bho[2:0] ssf we_l ce_l id[4:0] bhi[2:0] ssv ack tap ale_l fulo[1:0]/lho_1[1:0] fuli[6:0]/lhi_1[6:0] eot full logic full rst_l phs_l decode clk1x/clk2x mask array data array clk_mode block associated internal registers figure 2-1. ayama? 10000 block diagram control control and configuration pipeline internal registers par[1:0] parerr_l controller tms tdi tck trst_l tdo multi_hit n = 25 for cynse10512, 24 for 23 for cynse10256, CYNSE10128 parity and [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 12 of 153 figure 2-2 shows how an nse subsystem can be formed using a host asic, a bank of ayama 10000 devices and a bank of sram devices. it presents an example of ho w the nse subsystem is integrated in a s witch or router. the example also shows two possible ways of connecting the devices in the nse subsystem. in the associative set-up, t he host asic sends instructions to the nse. where applicable, the nse drives the sram inputs an d the sram then returns the requested data to the host asic. in the index set-up, the nse?s sram address information is rout ed back to the host asic. the host asic then interacts with the sram bank after it receives the result from the nse. figure 2-2. example of switch/router implementation using ayama 10000 switch processor switch fabric network line interface program memory system bus host asic ayama 10000 sram sram ayama 10000 host asic associative mode index mode bank bank bank bank or nse subsystem [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 13 of 153 3.0 device architecture overview 3.1 data array, mask array and table widths the ayama 10000 device consists of m 72-bit (m = 256k for cynse10512, 128k for cynse10256, 64k for CYNSE10128) storage cells referred to as data bits. there is also a mask cell corresponding to each data cell. a database entry includes bo th the data and mask cells. figure 3-1 shows the four possible table width sizes of the data and mask cells and the maximum possible table depth for each width. the ayama 10000 can be configured to contain tables of different widths in one device up to a maximum equal to 512k/256k/128k 72-bit entries. for example, a single ayama 10000 device can ha ve both a 5-tuple flow table and an ipv6 forwarding table. figure 3-2 shows a sample configuration of multiple table widths in a cynse10512 device. note: 1. 576-bit table configuration is only supported in the enhanced mode. data m/2 144-bit data masks m/4 288-bit data masks m 72-bit masks data masks m/8 figure 3-1. ayama 10000 database table widths m = 256k for cynse10512 128k for cynse10256 64k for CYNSE10128 576-bit [1] 32k 144 16k 288 64k 72 8k figure 3-2. multi-width database configuration example 576 [1] [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 14 of 153 3.2 data and mask addressing each 72-bit entry in the device can be accessed directly thr ough its address index. the data and mask arrays addresses are as shown in figure 3-3 . 3.3 successful search and multiple match arbitration during a search operation, the search data bit is masked wit h the corresponding global mask bit from the selected global mask register and the mask array bit before being compared to the data array entry bit to check for a match at that bit position (se e table 3-1 ). the entry with a match on every bit position results in a successful search. for exampl e, in order for a successful search within a device to make the device the local winner, all 72 -bit positions must generate a match for a 72-bit entry in 72 -bit- configured quadrants. the same applies to 144-bit, 288-bit, and 576-bit searches. the on-chip priority encoder selects the first matching entry in t he database that is nearest to memory address 0. an arbitrati on mechanism using a cascade bus determines th e global winning device amo ng the local winning devices in a search cycle. the global winning device then drives the output signals. when there is no successful sear ch, the device designated as the last dev ice (refer to section 5.3 for more information on last device designation) will drive the output signals. table 3-1. bit position match global mask bit mask array bit data array bit search key bit match result 0xxx1 10xx1 11001 11100 11010 11111 71 0 72 0 1 2 3 n - 1 287 0 72 72 3 2 1 0 7 6 5 4 n - 4 n - 3 n - 2 n - 1 72 72 143 0 72 72 1 0 3 2 5 4 7 6 n - 2 n - 1 72-bit configuration 288-bit configuration 144-bit configuration n n/4 n/2 575 0 72 72 3 2 1 0 11 10 9 8 n - 8 n - 7 n - 6 n - 5 72 72 576-bit configuration n/8 72 72 72 72 7 6 5 4 15 14 13 12 n - 4 n - 3 n - 2 n - 1 figure 3-3. addressing the ayama 10000 data and mask arrays n = 262144 for cynse10512 131072 for cynse10256 65536 for CYNSE10128 [1] [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 15 of 153 4.0 signals description table 4-1 lists and describes all ayama 10000 signals. table 4-1. ayama? 10000 signal description parameter type [2] description clocks and reset clk_mode i clock mode . selects the clock source for the device. when set to low, the device uses both clk2x and phs_l for its clock sources. when pulled high (v ddq_asic ), the device uses clk1x for its clock source (phs_l must be externally grounded). clk2x/clk1x i master clock . clk_mode selects either the clk2x or clk1x as the clock input signal. clk1x input signals are sampled on both rising and falling edges. output signals can be driven on both fa lling and rising depending on the operation and the device configuration. clk2x input signals are sampled on the rising edge. output signals are driven on the rising edge. phs_l i phase . an input signal that must switch at half the frequency of clk2x. this signal should be pulled low when the device is in clk1x mode. see section 5.6, ?clocks,? on page 42 . rst_l i reset . driving rst_l low initializes the device to the default state. the device becomes active stable 4 clk1x (8 clk2x) cycles af ter rst_l is driven high (90% threshold). configuration cfg_l i configuration . when cfg_l is set to low, the device will tristate dq[71:68]. id[4:0] i device identification . the binary-encoded device identification for a depth-cascaded system starts at ?00000? and goes up to ? 11110?. ?11111? is reserved as the broadcast address which selects all nses in the cascade. on a broadcast read, only the device with the ldev bit set to ?1? will respond. any id bit that is to be set high must be connected to v ddq_asic . asicsel i asic io select . when this signal is pulled high (1 .8v or 2.5v lvcmos), the command, data and cascade buses will operate in lvcmos mode. when tied to low, the buses will operate in hstl mode. signals affected by asicsel selection: clocks : clk2x/clk1x, phs_l, rst_l command and data : cmd[10:0], cmdv, dq[71:0], pa r[1:0], ack, eot, ssf, ssv, multi_hit cascade interface : lhi[6:0], lho[1:0], bhi[2:0], bh o[2:0], fuli[6:0], fulo[1:0], full sramsel i sram io select . when this signal is pulled high (1.8v or 2.5v lvcmos), the sram interface will operate in lvcmos mode. when tied to low, the interface will operate in hstl mode. signals affected by sramsel selection: sadr[25:0], ce_l, we_l, oe_l, ale_l hsvref0 i hstl reference voltage . when asicsel is set to gnd, this signal must be connected to the hstl reference voltage (vddq_asic/2). otherwise, they should be left floating. hsvref1 i hstl reference voltage . refer to hsvref0 description. parerr_l [3] o parity error . this signal is updated when there is a core parity error or dq bus parity error. it is an active-low open-drain signal that requires an external pull-up resistor to vddq_asic. this signal is valid only afte r the device is fully initialized. asic interface / command and data buses (lvcmos or hstl i/ii) cmd[10:0] i command bus . bit[10:2] contains the command para meters and bit[1:0] specifies the command. [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 16 of 153 cmdv i command valid . this signal indicates valid command in the cmd bus when set to high. dq[71:0] i/o address/data bus . this signal carries the following information: search operation: compare data (search key) sram pio operations: sram address other operations to register, data, and mask array regions: address and data par[1:0] i/o parity bus . these signals contain the even parity values for the dq bus. on the read return data, the nse generates the parity bi ts. on all other operations these bits are externally driven. bit [0] is the parity for all even dq signals. bit[1] is the parity for all odd dq signals. ack [4] t read acknowledge . this signal indicates that valid data is available on the dq bus during register, data, and mask array read operat ions, or that the data is available on the sram data bus during sram read operations. eot [4] t end of transfer . this signal indicates the end of burst transfer to the data or mask array during read or write burst operations. ssf [5] t search successful flag . when asserted, this signal indicates that the device is the global winner in a search operation. ssv [5] t search successful flag valid . when asserted, it indicates valid ssf value. in enhanced mode, this signal also indicates valid full and multi_hit values. multi_hit [5] o multiple hit flag . in a search operation, this signal indicates that there are multiple entries in the array or in the selected blocks that match the search key when it is set to 1. in a learn operation, it indicates that there are multiple free entries. in non-enhanced mode, it becomes valid 4 clk1x cycles after the command is issued. in enhanced mode, it becom es valid when ssv is 1. full t full flag . when high, it indicates that the table in the arra y or in the selected blocks (enhanced mode) is full. in the non-enhanced mode, it becomes valid 4 clk1x cycles after the command is issued. in the enhanced mode, it becomes valid when ssv is 1. high_speed1 i high speed 1 . this signal must be pulled high (v ddq_asic ) when the device operates at clk2x frequency above 166 mhz. high_speed2 i high speed 2 . this signal must be pulled high (v ddq_asic ) when the device operates at clk2x frequency above 200 mhz. sram interface (lvcmos or hstl i/ii) sadr[m:0] [5] t sram address . this bus contains address lines to access off-chip srams that contain associative data. in a cascaded system of multiple ayama 10000 nses, each corre- sponding sadr bit from all cascaded devices must be tied together. m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128. ce_l [5] t sram chip enable . this is the chip enable (ce) control for external srams. in a cascaded system of multiple ayama 10000 nses , ce_l of all cascaded devices must be tied together. this signal is then driven by only one of the devices. we_l [5] t sram write enable . this is the write enable control fo r external srams. in a cascaded system of multiple ayama 10000 nses, we_l of all cascaded devices must be tied together. this signal is then driven by only one of the devices. oe_l [5] t sram output enable . this is the output enable (oe) control for external srams. only the last device drives this signal (the device that has the lram bit set). ale_l [5] t address latch enable . when this signal is low, the addresses are valid on the sram address bus. in a cascaded system of multiple ayama 10000s, the ale_l of all cascaded devices must be tied together. this signal is then driven by only one of the devices. table 4-1. ayama? 10000 signal description (continued) parameter type [2] description [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 17 of 153 cascade interface (lvcmos and hstl) lhi[6:0] lhi_0[6:0] (mse=1) i local hit in/local hit in array 0 . these signals are inputs from upstream devices in a cascade that indicate whether there is a hit in the upstream/previous device(s). when multisearch is performed, lhi[6:0] becomes lhi_0[6:0] (local hit input signals for array 0). lho[1:0] lho_0[1:0] (mse=1) o local hit out/ local hit out array 0 . lho[1] and lho[0] are logically the same signal. one of these signal is connected to one in put on the lhi bus of the downstream devices in a cascade. when multisearch is performed, lho[1:0] bec omes lho_0[1:0] (loc al hit output signals for array 0). bhi[2:0] i block hit in . these signals are inputs from the la st device in the upstream blocks in a cascade that indicate whether there is a hit in the upstream/previous block(s). bho[2:0] o block hit out . these signals are logically the same signal. one of these signals is connected to one input on the bhi bus of the downstream devices in the downstream blocks. fuli[6:0] lhi_1_l[6:0] (mse=1) i full in/local hit in array 1 . each signal is driven by an upstream device?s fulo output in a block to generate the full signal for that block. during a search operation, these signals indicate whether an upstream device had a free entry for a future learn. when multisearch is performed, fuli[6:0] bec omes active low lhi _1_l[6:0] (local hit input signals for array 1). fulo[1:0] lho_1_l[1:0] (mse=1) o full out/local hit out array 1 . fulo[0] and fulo[1] are logically the same signal. one of these signal is connected to one input on the fulo bus of the downstream devices in a cascade. when multisearch is performed, fulo[1:0] be comes active low lhi_0_l[1:0] (local hit output signals for array 1). supplies v dd core supply : 1.2v. v dd_pll pll block supply : 1.2v. v ddq_asic asic and cascade interface i/o supply : 1.5v (hstl) or 1.8v/2.5v (lvcmos). v ddq_sram sram interfaced i/o supply : 1.5v (hstl) or 1.8v/2.5v (lvcmos). v ddq_jtag jtag test access port i/o supply : 2.5v (lvcmos). test access port tdi i test access port test data in. tck i test access port test clock. tdo t test access port test data out. tms i test access port test mode select. trst_l i test access port reset. notes: 2. i = input only, i/o = input or output, o = output only, t = three-state output. 3. the rise time of parerr_l will depend on the value of the pull-up resistance. sufficient delay should be allotted for in the error routine after clearing the parity error in the parity control register and before this pin is sampled as part of the next command. recommended external pull-up r esistance range: 4.7k ? to 47k ? . 4. require an external pull-down resistor such as 47k ? or 100k ? . 5. these signals will output at the rising edge of clk2x (both rising and falling edges of clk1x) in a multisearch operation. table 4-1. ayama? 10000 signal description (continued) parameter type [2] description [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 18 of 153 5.0 functional description 5.1 modes of operation ayama 10000 can operate in two differen t modes of operation: no n-enhanced and enhanced. the non-enhanced mode of operation is provided for backward compatibility with the cy nse70000 device family. the enhanced mode allows the ayama 10000 to utilize the featur es that can be used to lower powe r consumption, ease table manageme nt, increase data integrity and increase search throughput. these features are mini-key ? , soft priority ? , parity, and multisearch ? . the following subsections provide more information on each of the modes and features. the device powers-up in non-enhanced mode. a switch to en hanced mode and activation of the features require the user to configure internal registers with appropriate values. refer to section 5.4 for detailed information on the internal registers. table 5-1 lists the features and functi ons that are different betwe en the two modes of operation. 5.1.1 non-enhanced mode in the non-enhanced mode of operation, the ayama 10000 device is organi zed into 32/16/8 partitions (corresponds to cynse10512/256/128, respectively) that each can be configured to be 8k x 72, 4k x 144, or 2k x 288. the 576-bit table width configuration is not supported in this operation mode. the lsb of each 72-bit is designated to indicate whether that entry is u sed or not. when the entry is empty, that bit must be set to 0. when the entry is used , that bit must be set to 1. for example, in a 288-bit table a used entry will have bit[0], bit[72], bit[144], a nd bit[216] set to 1. when all bi t[0] are set to 1, the ayama 10000 will assert fulo[1:0] to ?11.? references are present throughout this document to indicates features that are applicable when device is in this mode. internal registers for conf iguration: config and cmd. 5.1.2 enhanced mode in enhanced mode, ayama 10000 is organized into 128/64/32 blocks (corresponds to cynse10512/256/128 respectively) of 2k x 72 which can also be configured into 1k x 144, 512 x 288, or 256 x 576. the mini-key, soft priority, parity, and multisearc h features can also be activated. each block has internal block re gisters associated to it that needs to be initialized before th e device goes into normal operation. figure 5-1 shows the general overview of the block registers association. references are present throughout this document to indicates features that are applicable w hen the device is in this mode. table 5-1. summary of non-enhanced and enhanced mode features and functions differences features/functions non-enhanced enhanced maximum search throughput 133 msps 266 msps multisearch? no yes soft priority? no yes mini-key? no yes parity no yes learn operation data fr om cmpr register; target data array; supports x72 and x144 table widths data from cmpr register or dq bus; target data or mask array; supports all table widths where to configure the table width config register bmr register table widths supported x72, x144, x288 x72, x144, x288, x576 data and mask array organization 32/16/8 8kx72-bit partitions for cynse10512/256/128 respectively 128/64/32 2kx72-bit blocks for cynse10512/256/128 respectively [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 19 of 153 5.1.2.1 mini-key the mini-key feature allows the device to power down blocks within the devic e that are not being selected to participate in the search operation. this results in lower power consumption. when a device has multiple tables, the block architecture of the dev ice combined with mini-key can be used to ease table expansion or re organization. there are four mi ni-keys that can be associated with each block ( figure 5-2 ) which supports each block to be a member of up to four logical tables. the block register that holds the mini-key values also includes the field that c onfigures the block to be of a certain table width. figure 5-2. mini-key register contents during a search operation, the search key width as well as the search mini-key are used to sele ctively activate certain blocks. a block will participate in the search operation only when the search width matches the block?s table width and the search mini - key matches one of the four mini-keys of the block. internal registers for conf iguration: cmd, cpr and bmr. 5.1.2.2 soft priority table management can become a time consuming process and slow down the performance of the system. in an edge router with multiple table of same widths in one or more ayama 10000 devi ces, that constantly update the entries, one table may become full very quickly. the time it takes to process table expans ion and data reorganization can be critical in a system that requir es high performance and quality of service. so ft priority feature in the ayama 10000 can help avoid that problem. for soft priorit y purposes, each 2kx72 block of data/mask a rray is arranged into four 512 x 72 sub-blocks. each s ub-block has a user-program- 2k mini-key register priority register 72 bits 72 bits figure 5-1. blocks and bl ock registers association parity register nfa register 2k mini-key register priority register parity register nfa register 2k mini-key register priority register parity register nfa register block 0 block 1 block n n = 127 for cynse10512 63 for cynse10256 31 for CYNSE10128 2k mini-key register mini-key0 mini-key1 table width mini-key2 mini-key3 72 bits [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 20 of 153 mable soft priority value that becomes part of the search ke y when soft priority feature is enabled. this feature eases the management of the tables, especially for tabl e expansion. each sub-block also has a priority valid bit that can be used to set the soft priority value of the sub-block to invalid state which will also prevent the sub-block from participating in a search oper ation. figure 5-3 shows the associations of the sub-blocks and soft priority. internal registers for configuration: cmd, cpr and bpr. 5.1.2.3 parity ayama 10000 introduces parity to provide additional protection for data integrity. parity checking can be performed both on the data transmission that passes through dq bus and the data stored in the core (data and mask arrays). the parity feature can be enabled through the parity register. dq bus and core parity checking can be independently enabled. when parity checking is enabled, a write operation ignores any masking and all bits are written as presented in the dq bus. even parity is used in the parity checking. for example, if ther e is an odd number of logic-1 bits in a word, the corresponding parity bit will be set high in order for the combination (word and parity bit) to have even parity. when an error is detected, the device will update the parity register and set the parity error flag (parerr_l) to report the er ror. parity status is not cascaded. however, parerr_l is an open-dr ain signal to allow signals from cascaded ayama 10000 devices to be connected together and provide cascaded parity error detection. theref ore, the ac timing parameters associated with the signal (rise time/fall time) will be dependent on the loading conditi ons. note that all parity status fields in parity and bpar registers needs to be cleared by the asic after fixing the errors. internal registers for configuration: parity and bpar. dq bus parity the dq bus is divided into even-bits and odd-bits groups for parity checking. parity bits of both even- and odd-bits groups are provided in the bidirectional par[1:0]. wh en the asic is driving the dq bus, the asi c must generate the parity bits. when the nse is driving the dq bus, the nse will generate the parity bits. when the asic is driving the dq bus, the nse will calculate the data stream parity and compar e it to par[1: 0]. when there is an error, the nse will update the pari ty register and set parerr_l to 0. parerr_l is valid on the (3+t) th cycle of latency for a read operation and (4+t) th cycle of latency for the other operations. t is th e cycle where the bus parity error is detected. when a dq bus parity error is detected, the nse must be reset and reinitialized. figure 5.4 shows the timing diagram of a dq bus parity error during a 288-bit search instruction. in cycle 1b the parity of the odd dq bits is shown to be ?1? while the corresponding parity bi t (par[1]) is ?0? (should be high for parity check to result in a ?0?).the parerr_l signal goes low 4 cycles after the error is detected. block 0 block 1 block 2 block n 2k x 72 512 x 72 sub-block 0 sub-block 1 sub-block 2 sub-block 3 priority 0 priority 1 priority 2 priority 3 v0 v1 v2 v3 n = 127 for cynse10512 63 for cynse10256 31 for CYNSE10128 figure 5-3. sub-blocks and soft priority associations [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 21 of 153 core parity the core includes a one-bit parity for each 72-bit entry in the data and mask arrays. when writing into the data or mask array, the nse will calculate and generate the one-bit parity for each 72 -bit data. each block also has a block-associated internal re gister to enable the parity checking for the block (bpar). when disabled, the block will ignore the read parity command. to issue the read parity command, the asic issues a read comm and and sets the parity field in the parameters sent through the dq bus as described in table 5-25 . core parity checking is performed in parallel on four adjacent 72-bit entries per pair of blocks. at the beginning of each parity o peration, an internal address counter is in cremented. the new incremented address is then used for the parity check operation. it will cycle through the data and mask arrays as well as odd and even blocks for both arrays for each read parity issued. if o ne or more parity errors are detected, the error is reported in t he block?s bpar register. then all errors are prioritized through an arbiter to select the highest priority parity error, which is then reported in the parity register. parerr_l will also be set t o 0 when there is a parity error. parerr_l is valid on the (5+tlsz) th cycle of latency. for example, with tlsz set to ?00? and the command is issued at cycle1, parerr_l will be valid on cycle6. re ad parity also responds to broadcast chipid selection. figure 5-5 shows the timing diagram of a core parity error during a read parity instruction. the parerr_l signal goes low 5 cycles after the e rror is detected. there are two basic flows for parity error re covery. the first flow is by reading the highest priority parity error address sto red in the parity register, fix the error, decreme nt the internal address counter and reissue read parity. the second flow is by readi ng the parity register to obtain the location, reading the bpar registers to locate blocks that has the error and then fixing thos e locations. cycle cycle cycle cycle cycle cycle 288-bit search 1 2 345 6 clk2x cmdv cmd[1:0] par[0] even dq cmd[10:2] a b phs_l cycle 7 cycle 8 cycle 9 cycle 10 a b odd bits odd dq bits par[1] odd odd even odd odd even even parerr_l incorrect value for par[1] tt+1t+2 t+3 t+4 figure 5-4. timing diagram of a dq bu s parity error (288-bit search, tlsz=00) [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 22 of 153 5.1.2.4 multisearch when multisearch is activated, the core is divided into two separate arrays. each array is organized into 64/32/16 blocks (corresponds to cynse10512/cynse10256/CYNSE10128, respectively ) of 2k 72-bit entries. each block can be configured to be of width x72, x144, x288, or x576. this separation allows a search operation to simultaneously perform the search across both arrays. the output signals will run at double data rate to effectively increase the throughput to a maximum of 266 million searches per second. each arra y can have multiple tables with different widt hs. single-search operation outputs are driven at the rising edge of clk1x. when the device has the multisearc h feature enabled and multisearch operation is issued (single- search can still be issued even when mult isearch is enabled), the output is driven at both rising and falling edges of clk1x (rising edge of clk2x). output from array 0 is driven at the rising edge while output from array 1 is driven at the falling edg e of clk1x. figure 5-6 shows an illustration of the multisearch operation. both arrays will use the same search key except for search oper ation on 72-bit wide tables. so does the selection of the global mask register (gmr) and comparand register (cmpr) as listed in table 5-2 . cycle cycle cycle cycle cycle cycle read parity 1 2 345 6 clk2x cmdv cmd[1:0] parerr_l dq cmd[10:2] a b phs_l cycle 7 cycle 8 cycle 9 cycle 10 figure 5-5. timing diagram of a core parity error (tlsz=00) t t+1 t+2 t+3 t+4 t+5 x72 x72 x576 search array 0 array 1 result0 result1 time x72 x144 x288 figure 5-6. multisearch operation overview [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 23 of 153 clk2x runs at twice the frequency of clk1x. ?a? refers to the first clk2x cycle in a clk1x cycle. ?b? refers to the second clk2 x cycle in a clk1x cycle. when multisearch is issu ed on x72 tables, array 0 will use the gmr provided in cycle 1 and array 1 wi ll automatically selects t o use the next-up gmr. for example, if gmr[0] is selected in cycle 1, gmr[1] will be selected automatically for array 1. array 0 uses the search key provided in cycle 1-a while array 1 uses the search key provided in cycle 1-b. when multisearch is issued on x288 tabl es, array 0 and array 1 will both use the same search ke y selected in cycle 1 and cycle 2 . the gmr selection for array 0 is done per cycle and array 1 automatically selects th e next up gmr register. for example, if gmr[6] is selected for the first 144 bits of array 0 in cycle 1, gmr[7] is automatically selected for the first 144 bits of arr ay 1. then if gmr[15] is selected for the second 144 bits of array 0 in cycle 2, gmr[0] is automatica lly selected for the second 144 bits of array 1. in all cases, the cmpr used in the sear ch operation for array 0 is the one sele cted in cycle 1 and the next up cmpr is automatically selected for array 1. internal register for configuration: cmd. 5.1.2.5 enhanced learn operation ayama 10000 extends the capability of the learn function to allow users to select the data source for the operation. the data c an be from the dq bus or one of the comparand (cmpr) registers. it also allows the data to be written to both the mask and data array while in non-enhanced mode it allows the data to be written only to the data array. internal register for configuration: cmd. 5.2 i/o interfaces data flows in and out of the device through three separate i/o interfaces: asic, sram and cascade interface. section 4.0, ?signals description,? on page 15 lists the signals that are part of each interface. input signals ar e registered on the rising edge and falling edge of clk1x or rising edge of clk2x. output signals are driven out on the rising edge of clk1x or rising edge of clk2x when phs_l is low. an exception is when multisearch oper ation is activated, the output will be driven out on both edges of clk1x or rising edge of clk2x. refer to section 5.6 for more information on clock signals. figure 5-7 shows an example of asic, nses and srams i/o interconnects. the sram interface outputs may be connec ted to sram devices in associative applications mode or back to the asic in index applications mode. table 5-2. selection of search key, gmr, and cmpr in multisearch operation search width array 0 array 1 gmr key srr gmr key srr x72/x72 1: gmr 1: a 1: cmpr 1: gmr+1 1: b 1: cmpr+1 x144/x144 1: gmr 1: a, b 1: cmpr 1: gmr+1 1: a, b 1: cmpr+1 x288/x288 1: gmr 1: a, b 1: cmpr 1: gmr+1 1: a, b 1: cmpr+1 2: gmr 2: a, b 2: gmr+1 2: a, b x576/x576 1: gmr 1: a, b 1: cmpr 1: gmr+1 1: a, b 1: cmpr+1 2: gmr 2: a, b 2: gmr+1 2: a, b 3: gmr 3: a, b 3: gmr+1 3: a, b 4: gmr 4: a, b 4: gmr+1 4: a, b [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 24 of 153 internal register for configuration: hardware. 5.2.1 asic interface the asic interface includes all signals for data that come s in from and out to a system?s processing unit, which could be an application specific (asic) or a more generic network processing unit (npu and ncp). it supports lvcmos and hstl i/o standards. lvcmos allows the i/o signals to run at a rate of up to 100 mhz (clk1x; double data rate in multisearch operation). with hstl, the i/o signals can run at a rate of up to 13 3 mhz (clk1x; double data rate in multisearch operation). the asic interface includes the command and dq bus signal group. cmd[10:0] carries the command and its associated parameter. dq[71:0] is used for data transfer to and from t he database entries, which are comprised of data and mask fields tha t are organized as data and mask arrays. the dq bus carries search data (of the data and mask arrays and internal registers) during the search command as well as the address and data durin g read and/or write operations. the dq bus also carries address information for the direct accesses to the external sram. 5.2.2 sram interface the sram interface includes output only sign als that are used to interact with sram me mory devices. as with the asic interface, it supports lvcmos and hstl i/o standards. lvcmos allows the i/o signals to run at a rate of up to 100 mhz (200-mhz double data rate with multisearch operation). with hstl, the i/o signals can run at a rate of up to 133 mhz (266-mhz double date rate with multisearch operation). 5.2.3 cascade interface the cascade inte rface is used for cascading multiple ayama 10000 devices in a system. it supports lvcmos and hstl i/o standards that can run up to 133 mhz in all operation modes. the cascade interface power supply is the same power supply that the asic interface uses. thus the sele ction of the i/o standard used for the casc ade interface depends on the i/o standard selected for the asic interface. when multiple nses are cascaded to create large databases, th e data being searched is presented to all nses in the cascaded system simultaneously. if multiple matches occur, arbitration lo gic on the nses will enable the winning device (the one with a matching entry closest to address 0 of the cascaded database) to drive the sram bus . user can set the default device to respond to an operation when a search operation does not result in a search hit. refer to section 5.3 for more information. cascade cascade sram asic ayama 10000 cascade cascade sram asic ayama 10000 cascade cascade sram asic ayama 10000 cascade cascade sram asic ayama 10000 from asic to srams (associative) to asic (index) or figure 5-7. ayama 10000 i/o interfaces [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 25 of 153 5.3 output signals default driver/last device designation (lram and ldev) when nses are cascaded using multiple ayama 10000 devices, the sadr, ce_l, and we_l (three-state signals) are all tied together. in order to eliminate external pull-up and pull-downs , one device in a bank is designated the default driver. for non - search or non-learn cycles (see subsection 6.6, ?learn command? ) or search cycles with a global miss, the sadr, ce_l, and we_l signals are driven by the device wit h the lram bit set. it is important that only one device in a bank of cascaded nses have this bit set. failure to do so will cause contention on th e sadr, ce_l, and we_l, and can potentially cause damage to the device(s). similarly, when nses using multiple ayama 10000 devices are casc aded, ssf and ssv (also thre e-state signals) are tied together. in order to eliminate external pull-up and pull-downs, one device in a bank is designated as the default driver. for non- search cycles or search cycles with a global miss, the ssf and ssv signals are driven by the device with the ldev bit set. it i s important that only one device in a bank of cascaded nses have this bit set. failure to do so will cause contention on the ssv and ssf, and can potentially c ause damage to the device(s). 5.4 registers table 5-3 provides an overview of all the ayama 10000 internal regist ers. each register is 72 bits wide. the ayama 10000 contains sixteen pairs of comparand storage registers, sixteen pairs of gl obal mask registers, eight search status index registers, sixt een search control parameters registers, sixteen search result r egisters and one each of command, information, burst read, burst write, next-free address register, partition configuration, hardw are and parity control registers. each of the blocks in the ns e device (128/64/32 2kx72 blocks in cynse10512/ 256/128 respectively) also has one each of block mini-key, block priority, block parity and block next-free address registers. there are also four block priority register aliases registers for each block prio rity register that allows an alternative way to update the block priority registers. the registers are presented in ascending addres s order. each register group is then described in the following subs ections. reserved fields in the registers are read as 0s. whe n writing to the registers, all reserved fi elds must be written with 0s, unless specifie d otherwise in the field?s description. table 5-3. list of internal registers address (decimal) abbreviation type (read/write) description 0?31 cmpr0?15 r comparand register . sixteen cmpr pairs (144 bits per pair) that store comparands from the dq bus during a search operation for later use with the learn command. see section 5.4.1 . 32?47 96?111 gmr0?7 gmr8?15 r/w global mask register . sixteen gmr pairs (144 bits per pair) used for global mask bits on the dq bus for all commands. see section 5.4.2 . 48?55 ssr0?7 r search successful register . these registers store the result of search opera- tions. see section 5.4.3 . 56 command r/w command register . this register contains control fields that determine how the nse operates. see section 5.4.4 . 57 info r information register . this read-only register contains static information about the nse device. see section 5.4.5 . 58 rburreg r/w burst-read register . this register contains the starting address and count for a read burst operation. see section 5.4.6 . 59 wburreg r/w burst-write register . this register contains the starting address and count for a write burst operation. see section 5.4.7 . 60 nfa r next-free address register . this register contains the index of the next-free entry when the device is in the non-enhanced mode (enhanced mode uses srr registers to store the next-free entry information). see section 5.4.8 . 61 config r/w partition configuration register . this register contains the partition type bits when the nse device operates in the non-enhanced mode. it is not used in the enhanced mode. see section 5.4.9 . 62 hardware r/w hardware register . this register contains i/o drive strength settings. see section 5.4.10 . 63 parity r/w parity control register . this register contains the control and address for parity checking of the core and registers. see section 5.4.11 . 64?79 cpr0?15 r/w control register . these registers provide mini-key and soft priority for the associated operation. see section 5.4.12 . 80?95 srr0?15 r search result register . these registers provide information of the next-free entry when the device is in the enhanced mode. (non-enhanced mode uses the nfa register to store the next-free entry information.) see section 5.4.13 . [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 26 of 153 5.4.1 comparand register (cmpr) the device contains 16 pairs of comparand registers (one pair is 144 bits) dynamically selected in every search operation to st ore the comparand presented on the dq bus. the device may later use these registers when it execut es a learn operation. search and learn commands specify the comparand registers in pairs. the ayama 10000 devi ce stores the search command?s cycle a comparand in the even-numbered regist er and the cycle b comparand in the o dd-numbered register, as shown in figure 5-8 . for wider width keys, pairs of comparand registers are concatenate d together. the concatenation of the registers must be done by the user. on a 72-bit operation, both halv es of the comparand register must be l oaded with the same value. when performing multisearch operation, the nse requires two comparand registers for an operation. the first comp arand register is specified in the command and the nse automatically selects the comparand r egister one index higher than the command specified register. when the device powers-up, the cmpr registers are initialized to 0. 5.4.2 global mask register (gmr) the device contains 16 pairs of gmrs (one pair is 144 bits) dy namically selected in every sear ch operation to select the search subfield. the addressing of t hese registers is shown in figure 5-9 . the gmr index supplied on the command bus selects one of the sixteen pairs of global masks during search and write operati ons. in 72-bit search and writ e operations, the host asic must program both the even and odd mask register s with the same values. for a multisearch operation, two separate gmrs are used in the operation. the first one is specified in the command and the second one is one index higher. each mask bit in the gmrs is used during search and write operat ions. in a search operation, setting the mask bit to 1 enables while setting the mask bit to 0 disables compares at the corresp onding bit position (forced match). in write operations to the data or mask array, setting the mask bit to 1 enables write while setting the mask bit to 0 disables write at the corresponding bit position. write operation to internal registers does not use the gmr to mask the data and ignores the gmr selection when the command is issued. when the device powers-up, the gmr registers are initialized to 0. figure 5-9 below shows each portion (even, odd) of each gmr, and what address (in binary) is required to access that register. 112?1023 ? ? reserved . 1024 bmrx r/w block mini-key register . this register holds the four mini-keys associated with a block. there is one bmr per block. see section 5.4.14 . 1025 bprx r/w block priority register . this register holds the four sub-block priorities. there is one bpr per block. see section 5.4.15 . 1026 bparx r/w block parity register . this register contains the control and status bits for controlling and detecting parity errors for a block. there is one bpar per block. see section 5.4.16 . 1027 bnfax r block next-free address register . this register contai ns the next-free entry information for the block that it is asso ciated with. there is one bnfa per block. see section 5.4.17 . 1028?1031 bpra0x? bpra3x r/w block priority register aliases . these locations are aliases for the corre- sponding bprx. see section 5.4.18 . table 5-3. list of internal registers (continued) address (decimal) abbreviation type (read/write) description 143 0 72 72 1 0 3 2 5 4 7 6 30 31 index 0 15 1 address figure 5-8. comparand register selection during search and learn instructions [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 27 of 153 5.4.3 search successful register (ssr) the device contains eight search successful registers (ssr) to hold the index of the location at which a successful search occurred. the format of each ssr is described in table 5-4 . the search command specifies which ssr stores the index of a specific search command in cycle b of the search instruction. subsequently, the host asic can use this register to access that data array, mask array, or external sram using the index as part of the indirect access address. the selected register is updat ed when the device performs a search operat ion regardless of the operation modes. 03233 13435 23637 33839 44041 54243 64445 74647 89697 99899 10 100 101 11 102 103 12 104 105 13 106 107 14 108 109 15 110 111 143 72 72 0 figure 5-9. addressing the global mask register array gmr index even odd 7 15 23 0 39 47 55 31 63 71 index gval val n = 15 for CYNSE10128 figure 5-10. search successful register n = 16 for cynse10256 n = 17 for cynse10512 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 28 of 153 5.4.4 command register (command) table 5-5 describes the command register fields. this register is expe cted to be initialized by the user right after reset before performing any read, write, learn, search, or parity operations and thereafter not changed during normal operation. the user must also wait for at least 32 clk2x cycles after a write to the command register before issuing the next command. table 5-4. search successf ul register description field range (decimal) initial value (binary) description index [n:0] 0 index . this is the address of the 72-bit entry w here a successful search occurs. this index is updated if the device is either a local or global winner in a search operation. n = 17 for cynse10512, 16 for cynse10256, 15 for CYNSE10128. if a hit occurs in a 144-bit table, the leas t-significant bit (lsb) is cleared to 0. if a hit occurs in a 288-bit table, the two lsbs are cleared to 0. if a hit occurs in a 576-bit table, the three lsbs are cleared to 0. [29:n + 1] reserved . gval [30] 0 global valid . valid only in enhanced mode. it is updated when the device performs a search operation. it is set to 1 when there is no hit anywhere in the cascade and this device is the last one in the cascade (ldev field in cm d register is set to 1). otherwise it is cleared to 0. when set to 1, the device is responsible for responding to broadcast pio operation. val [31] 0 valid . this field is updated when the device performs a search operation. it is set to 1 only when the device is a global winner. otherwise it will be cleared to 0. [71:32] reserved . table 5-5. command register description field range (decimal) initial value (binary) description srst [0] 0 software reset . if set to 1, this bit resets the devi ce with the same effect as a hardware reset. internally, it generates a reset pulse la sting for eight clk2x cycles. this bit automat- ically resets to 0 after the reset pulse is deasserted. deve [1] 0 device enable . if 0, it keeps the sram bus (sa dr, we_l, ce_l, oe_l and ale_l), ssf, and ssv signals in a three-state condition and forces the cascade interface output signals lho[1:0] and bho[2:0] to 0. it also keeps the dq bus in input mode. the purpose is to make sure that there are no bus contentions when the device powers up. set this bit to 1 when the device is ready for operation. tlsz [3:2] 10 table size . this field increases the pipeline latenc y of the search and learn operations as well as the read and write accesses to the sram. once programmed, it is expected to not be changed. affected signals in both enhanced and non-enhanced modes: sadr, ce_l, oe_l, we_l, ale_l, ssv, ssf, and ack. affected signals only in enhanced mode: full and multi_hit. latency in number of clk cycles: ?00?: 4 cycles ?01?: 5 cycle ?10?: 6 cycles ?11?: reserved/invalid when high_speed1 is set to 1, ?00? is not supported. when high_speed2 is se t to 1, ?00? and ?01? are not supported. 7 15 23 0 39 47 55 31 63 71 srst deve hlat tlsz ldev lram cfga ben en lrn mse emode figure 5-11. command register [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 29 of 153 hlat [6:4] 000 latency of hit signals . this field adds latency to the ssf, ssv, full and multi_hit signals (in addition to the latency of tlsz) during a search operation and ack signal during sram read accesses as listed below: 000: 0 100: 4 001: 1 101: 5 010: 2 110: 6 011: 3 111: 7 ldev [7] 0 last device in the cascade . when set, the device is the last device in a cascaded and is the default driver for t he ssf and ssv signals. in the event of a search failure, the device with this bit set drives the hit signals as follows: ssf = 0 (binary), ssv = 1 (binary). in an operation other than search, the de vice with this bit set drives the hit signals as follows: ssf = 0 (binary), ssv = 0 (binary). when multiple devices are cascaded, one of the devices must have ldev set to 1. lram [8] 0 last device on the sram bus . when set to 1, this is the last device on the sram bus in a cascade and is the default driver for the sadr, ce_l, we_l, and ale_l signals. in cycles where none of the ay ama 10000 devices in a cascade drive these signals, this device drives the signals as follows: for cynse10512: sadr = 0x1ffffff for cynse10256: sadr = 0xffffff for CYNSE10128: sadr = 0x7fffff for cynse10512/256/128: ce_l = 1 we_l = 1 ale_l = 1 the device with this field set to 1 always drives oe_l. when multiple devices are cascaded, one of the devices must have lram set to 1. cfga [24:9] 0 database configuration . the field is an alias for the first ei ght pairs of partition configuration bits of the configuration register. reading and writ ing this field is reflec ted in the configuration register and vice versa. this field is only used when the device operates in the non-enhanced mode. [55:25] reserved . ben [56] 0 dq bus parity enable . when set to 1, it enables parity checking on the data transferred through dq bus. en [57] 0 core parity enable . when set to 1, it enables core parity checking. [60:58] reserved. lrn [61] 0 enhanced learn enable . when set to 1, it allows the user to select the data source for the learn operation from either the dq bus or one of the cmprs. it also allows the user to select whether the write is to the data or the mask array. this field is valid in the enhanced mode. mse [62] 0 multisearch enable . when set to 1, it activates support for multisearch operation. the sram output operates at clk2x rate instead of clk1x. this field is valid only when the emode field of command register is set to 1. emode [63] 0 enhanced mode . when set to 1, the device operates in the enhanced mode. when cleared to 0, the device operates in the non-enhanced mode. [71:64] reserved . table 5-5. command register description (continued) field range (decimal) initial value (binary) description [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 30 of 153 5.4.5 information register (info) table 5-6 describes the information register fields. 5.4.6 read burst address register (rburreg) table 5-7 shows the read burst address register fields. these mu st be programmed before issu ing a burst-read operation. table 5-6. information register description field range (decimal) initial value (binary) description rev [3:0] 0001 device revision number . impl [6:4] 001 implementation number . reserved [7] 0 reserved . devid [15:8] 0001 0100 device identification number for CYNSE10128 . 0001 0101 device identification number for cynse10256 . 0001 0110 device identification number for cynse10512 . manid [33:16] 00 00000 000 1101 1100 manufacturer id . reserved [71:34] reserved . table 5-7. read burst register description field range (decimal) initial value (binary) description index [n:0] 0 index . this field is used to identify the starting address of the data or mask array in a burst- read operation. the nse w ill automatically increment t he value by one after each successive read of the data or mask array. it must be reinitialized before the next burst- read operation. n = 17 for cynse10512, 16 for cynse10256, 15 for CYNSE10128. [18:m] reserved . m = 18 for cynse10512, 17 for cynse10256, 16 for CYNSE10128. blen [27:19] 0 length of burst access . the device provides the capability to read from 4 to 511 locations in a single burst. the nse automatically decr ements the value by one after each successive reading of the data or mask array. it must be reinitialized before the next burst-read operation. [71:28] reserved . 7 15 23 0 39 47 55 31 63 71 rev impl devid manid figure 5-12. information register n = 16 for cynse10256 n = 15 for CYNSE10128 n = 17 for cynse10512 7 15 23 0 39 47 55 31 63 71 index blen figure 5-13. read burst register n = 15 for CYNSE10128 n = 16 for cynse10256 n = 17 for cynse10512 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 31 of 153 5.4.7 write burst address register (wburreg) table 5-8 describes the write burst address register fields. these must be programmed before issu ing a burst-write operation. 5.4.8 next-free address register (nfa) the nfa register is used only when the device operates in the non-enhanced mode. the nfa register?s index field ( table 5-9 ) holds the address of the highest priority fr ee entry in the table. when the table is full, the index field will be set to all 1 s. when all entries in the device is full, the ayam a 10000 will assert fulo[1:0] to ?11?. table 5-8. write burst register description field range (decimal) initial value (binary) description index [n:0] 0 index . this field is used to identify the starting address of the data or mask array in a burst-write operation. the nse will automatically increment the value by one after each successive writ e of the data or mask array. it must be reinitialized before the next burst-write operation. n = 17 for cynse10512, 16 for cynse10256, 15 for CYNSE10128. [18:m] reserved . m = 18 for cynse10512, 17 for cynse10256, 16 for CYNSE10128. blen [27:19] 0 length of burst access . the device provides the capability to write from 4 to 511 locations in a single burs t. the nse automatically decrements the value by one after each successive writin g of the data or mask array. it must be reinitialized before the next burst-write operation. [71:28] reserved . table 5-9. nfa register description field range (decimal) initial value (binary) description index [n:0] 0 index . the address index of the next-free entry location. n = 17 for cynse10512, 16 for cynse10256, 15 for CYNSE10128. [71:m] reserved . m = 18 for cynse10512, 17 for cynse10256, 16 for CYNSE10128. 7 15 23 0 39 47 55 31 63 71 index blen n = 15 for CYNSE10128 n = 16 for cynse10256 n = 17 for cynse10512 figure 5-14. write burst address register 7 15 23 0 39 47 55 31 63 71 index n = 15 for CYNSE10128 n = 16 for cynse10256 n = 17 for cynse10512 figure 5-15. next-free address register [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 32 of 153 5.4.9 configuration register (config) the config register is valid only when th e device operates in the non-enhanced mode. ta ble 5-1 0 describes the information register fields. table 5-10. configuration register description field range (decimal) initial value (binary) description cfg [n:n-1] [n-2:n-3] ... [1:0] n = 63 for cynse10512, 31 for cynse10256, 15 for CYNSE10128. 0 partition configuration . in the non-enhanced mode, ayama 10000 is internally divided into 32/16/8 partitions corresponding to cynse10512/256/128 respec- tively. each two bits configures one partition as encoded below: 00: 8k 72 01: 4k 144 10: 2k 288 11: disabled (does not reduce power consumption in a search operation) bit[1:0] configures the first partition, bit[ 3:2] configures the second partition and so on. bit [15:0] of this register is aliased in bit[24:9] of the command register. modifi- cation to bit[15:0] of this field will affect the cfga field in the command register and vice versa. reserved [71:n + 1] reserved . 7 15 23 0 39 47 55 31 63 71 cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cynse10512 7 15 23 0 39 47 55 31 63 71 cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cfg cynse10256 7 15 23 0 39 47 55 31 63 71 cfg cfg cfg cfg cfg cfg cfg cfg CYNSE10128 figure 5-16. configuration register [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 33 of 153 5.4.10 hardware register (hardware) the hardware register controls the drive strength of the groups of signals as listed in section 6.0 . table 5-11 shows the fields that control each of the group and the output signals associated with it. table 5-11. hardware register description field range (decimal) initial value (binary) description [1:0] reserved . iojtag [3:2] 11 jtag i/os . sets the drive strength for the i/o. by default it is set to ?11?. the following output signal is part of this group: tdo. the lvcmos i/o drive strength fo r encoding is as listed below: 00: 2 ma 01: 8 ma 10: 16 ma 11: 24 ma (v ddq = 2.5v); 20 ma (v ddq = 1.8v) the hstl i/o drive strength fo r encoding is as listed below: 00: 8 ma (hstl i) 01: reserved 10: reserved 11: 17 ma (hstl ii) iocas [5:4] 11 cascade i/os . the following output signals are part of this group: lho, bho and fulo. refer to iojtag above for i/o drive strength encoding. iosram [7:6] 11 sram i/os . the following output signals are part of this group: sadr, ce_l, we_l, oe_l and ale_l. refer to iojtag above for i/o drive strength encoding. iodq [9:8] 11 command and dq bus i/os . the following output signal s are part of this group: dq, ack, eot, ssf, ssv, par, parerr_l, multi_hit, and full. refer to iojtag above for i/o drive strength encoding. [63:10] reserved . [71:64] 0 reserved . this field must be set to 0. 7 15 23 0 39 47 55 31 63 71 iocas iosram figure 5-17. hardware register iodq iojtag [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 34 of 153 5.4.11 parity control register (parity) table 5-12 describes the parity control register fields. this register is only active when the device is in the enhanced mode. table 5-12. parity control register description field range (decimal) initial value (binary) description index [18, n:0] 0 index . this field contains the highest priority parity error index. when a parity error is detected, the global priority encoder selects the highest priority parity error out of the entire core. note that if another parity operation is performed, this field is updated based upon that operation. n = 17 for cynse10512, 16 for cynse10256 (bit [17] is reserved), 15 for CYNSE10128 (bits [17:16] are reserved). bit[18] is used to indicate whether a mask (=1) or data (=0) entry contained the error. [27:19] reserved . bmulti [28] 0 multi dq parity error status bit . this field is set to 1 when multiple errors were detected during a bus transfer. it is also set to 1 when new parity error occurs and berr is set. this bit can only be cleared by a user write. berr [29] 0 dq parity error status bit . this bit is set when a parity error is detected during a data transfer across the dq bus. this bit c an only be cleared by a user write. multi [30] 0 multi-parity error status bit . this bit is set when more than one parity error in the core is detected during the parity operation. it also updates when a new parity error occurs and err is set. this bit can only be cleared by a user write. err [31] 0 parity error status bit . this bit is set when any parity error in the core is detected during the parity operation. this bit can only be cleared by a user write. adr [50, m:32] 0 current address . after a parity check, the address in this field is incremented and is ready for the next address to check for parity. when the parity operation finishes and an error is detected, assuming no intervening new parity oper ations, this field will point to the next entry address to be checked. bit[50] selects between mask (=1) or data (=0) array. as the address is incremented, this bit is treated as the lsb a nd toggles before bit[34]. bit[33:32] are always 0 because read parity operation checks 4 adja cent 72-bit entries. m = 49 for cynse10512, 48 for cynse10256 (bit [49] is reserved), 47 for CYNSE10128 (bits [49:48] are reserved). [71:51] reserved . 7 15 23 0 39 47 55 31 63 71 index multi err adr berr bmulti figure 5-18. parity control register n = 15 for CYNSE10128 n = 16 for cynse10256 n = 17 for cynse10512 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 35 of 153 5.4.12 control register (cpr[0:15]) these registers are active only when the device is in the en hanced mode. during a search operation, selecting a gmr will automatically select one of the cprs to participate in the search as shown in figure 5-19 . table 5-13 shows the fields of the cpr. table 5-13. control register field index (decimal) initial value (binary) description [31:0] reserved . priority [39:32] 0 software priority (soft priority) . this field contains the software priority for the associated command. smaller numeric value is higher in priority. 0x00 is the highest priority and 0xff is the lowest priority. mini-key [47:40] 0 mini-key . this field contains the mini-key to be used for the associated command. flg [48] 0 soft priority comparison flag . when set to 1, search comparison is with entries that has soft priority value eq ual to or higher (lower priority) than priority. when set to 0, comparison is only with equal value. [71:49] reserved . 0640 1651 2662 3673 4684 5695 6706 7717 8728 9739 10 74 10 11 75 11 12 76 12 13 77 13 14 78 14 15 79 15 cpr addr gmr index figure 5-19. selection of the cpr through gmr index cpr index 7 15 23 0 39 47 55 31 63 71 mini-key priority flg figure 5-20. control register [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 36 of 153 5.4.13 search result register (srr[15:0]) the srr register is only active when the device is in the enhanced mode. it contains status information about where the next- free entry is and what kind of entry it is. there are sixteen srrs; one srr asso ciated with one cmpr. the ssr is updated on a search operation regardless of hit or miss. two srrs are used in one search operation when mse is set. the second srr is automatically selected to be the register one index higher. table 5-14 below details the srr fields. table 5-15 below shows the different parts of the index field of the srr. table 5-14. search result register field index (decimal) initial value (binary) description index [n:0] 0 index . this field contains the hit or miss index inside the core. n = 17 for cynse10512, 16 for cynse10256, 15 for CYNSE10128. [23:m] reserved . m = 18 for cynse10512, 17 for cynse10256, 16 for CYNSE10128. mini-key [31:24] 0 mini-key . this field contains a copy of the mini-key value selected for the search operation. the value comes from the selected cpr. priority [39:32] 0 soft priority . this field holds the priority value of the sub-block where a successful search occurs. otherwise it holds the priority of the next-free entry sub-block. if there are no free entries, this fiel d is set to the selected cpr? s soft priority value. this field is not valid when status value is taken. status [43:40] 0 next-free entry status . this field contains the status information for the next-free entry. the status value is encoded as described below: 0000: single match. search hit and there is a single match. 0010: single free entry. search miss and there is a single free entry. 0100: single free sub-block. search mi ss and there is a single free sub-block. 0110: single free block. search miss and there is a single free block. 0001: multiple matches. search hi t and there are multiple matches. 0011: multiple free entries. search miss and there are multiple free entries 0101: multiple free sub-blocks. search mi ss and there are multiple free sub-blocks. 0111: multiple free blocks. search mi ss and there are multiple free blocks. 1000: taken. search miss a nd there are no free entries. [62:44] reserved . flg [63] 0 flag . when set to 1, this flag indicates that a search operation resulted in a miss, this device has a free entry and the upst ream devices in a cascade have a search miss with no free entries reported. note that a device with no free entries can still have free blocks or sub-blocks. [71:64] reserved . table 5-15. srr?s index composition based on status status index[17:11] index[10:9] index[8:0] hit block id sub-blo ck id hit entry index free entry block id sub-block id free entry index free sub-block block id sub-block id all zeros free block block id all zeros all zeros taken undefined undefined undefined 7 15 23 0 39 47 55 31 63 71 mini-key priority status index flg figure 5-21. search result register n = 15 for CYNSE10128 n = 16 for cynse10256 n = 17 for cynse10512 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 37 of 153 5.4.14 block mini-key register (bmr) the bmr is only accessible when the device is in the enhanced mode. there is one bmr for each block in the device. the following table ( table 5-16 ) shows the bmr fields. table 5-16. block mini-key register description field range (decimal) initial value (binary) description nes [1:0] 0 nse entry size . this field selects the entry width for the associated block. a search operation that is of different size than the nes will cause the block to not participate in the search. the nes encoding is as follows: 00: 72-bit 01: 144-bit 10: 288-bit 11: 576-bit for proper free-entry address computation, this nes field must be set before initializing the entries in a block. the entries of a block must then be initialized to a known value before accessing the block. [31:2] reserved . mini-key3 [39:32] 0 mini-key #3 . there are four mini-key fields in each bmr. when an operation occurs, all four fields are checked against the mini-key in the selected cpr by the command. if there is a match, the associat ed block is enabled to participate in the operation. mini-key2 [47:40] 0 mini-key #2 . see mini-key #3 description. mini-key1 [55:48] 0 mini-key #1 . see mini-key #3 description. mini-key0 [63:56] 0 mini-key #0 . see mini-key #3 description. [71:64] reserved . 7 15 23 0 39 47 55 31 63 71 mini-key3 nes mini-key2 mini-key1 mini-key0 figure 5-22. block mini-key register [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 38 of 153 5.4.15 block priority register (bpr) the bpr is only accessible when the device is in the enhanced mode. there is one bpr for each block in the device. for each priority in the bpr, there is an alias address (block priority re gister address) which allows individual priorities to be updat ed. table 5-17 shows the bpr fields. table 5-17. block priori ty register description field range (decimal) initial value (binary) description priority3 [7:0] 0 soft priority #3 . there are four priority fields in each bpr. each priority represents the priority of a sub-block located within the bloc k associated with this register. priority value of 00 (hex) is highest and ff (hex) is lowest in priority. the addresses in a block associated with each soft priority is as follows: entry index 0 to 511: priority0 entry index 512-1023: priority1 entry index 1024-1535: priority2 entry index 1536-2047: priority3 priority2 [15:8] 0 soft priority #2 . see soft priority #3 description. priority1 [23:16] 0 soft priority #1 . see soft priority #3 description. priority0 [31:24] 0 soft priority #0 . see soft priority #3 description. [59:32] reserved . v3 [60] 0 v #3 . there are four v fields in each bpr. each field represent the valid bit for a sub-block within the block associated with this register. if th is bit is set to 1 and the soft priority in the cpr selected by the operation matches, t he associated sub-block will participate in the operation. if this bit is set to 0, the asso ciated sub-block will not participate in a search operation. v2 [61] 0 v #2 . see v #3 description. v1 [62] 0 v #1 . see v #3 description. v0 [63] 0 v #0 . see v #3 description. [71:64] reserved . 7 15 23 0 39 47 55 31 63 71 priority3 v3 priority2 priority1 priority0 v2 v1 v0 figure 5-23. block priority register [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 39 of 153 5.4.16 block parity register (bpar) the bpar is only accessible when the device is in the enhanc ed mode. there is one bpar for each block in the device. table 5- 18 shows the bpr fields. 5.4.17 block nfa register (bnfa) the bnfa is only accessible when the device is in the enhanced mode. there is one bnfa for each block in the device. table 5- 19 shows the bnfa fields. table 5-18. block parity register description field range (decimal) initial value (binary) description perr [3:0] 0000 parity error . this field contains the status of a parity operation. it is set to 1 when any parity error is detected during the parity operation on the associated block. each bit corresponds to one of the four x72 entries checked during the parity operation. bit[0] corresponds to the lowest address. this field is sticky, i.e., it can only be clear ed by a user write to the register. this field contains only this block?s status. to cl ear this bit, the user must write a ?1? to this bit location. writing a ?0? wi ll preserve the old value. [30:4] reserved . en [31] 0 enable parity checking . this field enables parity checking for the associated block. when set to 1, the associated block will participate in parity operation. [71:32] reserved . table 5-19. block nfa register description field range (decimal) initial value (binary) description nfa3 [8:0] 0 next-free address for sub-block #3 . this field contains the address/index of the next- free entry within the sub-block of the block associ ated with this register. if the entry size is larger than x72, the least significant bits will be set to 0 as follows: x144: nfax[0] = ?0?, x288: nfax[1:0] = ?00?, x576: nfax[2:0] = ?000?. [13:9] reserved . multi3 [14] 1 multiple free entries in sub-block #3 . this field contains the multiple free entry status. if there are multiple free entries in t he sub-block, this bit is set to 1. f3 [15] 0 free entry in sub-block #3 . this field indicates the sub-block full status. if this field is set to 1, the sub-block is full and there are no free entries. if the field is set to 0, the sub-block is not full and there is a free entry. nfa2 [24:16] 0 next-free address for sub-block #2 . see nfa3 description. [29:25] reserved . multi2 [30] 1 multi free entry in sub-block #2 . see multi3 description. f2 [31] 0 free entry in sub-block #2 . see f3 description. 7 15 23 0 39 47 55 31 63 71 en perr figure 5-24. block parity register 7 15 23 0 39 47 55 31 63 71 nfa3 nfa2 nfa1 nfa0 f0 multi0 f1 f2 f3 multi1 multi2 multi3 figure 5-25. block nfa register [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 40 of 153 5.4.18 block priority register aliases (bpra) the bpra is only accessible when the device is in the enhanc ed mode. there are four bpras for each block. these pseudo registers provide an alternate means to update the associated block?s bpr. the fiel ds of these bpras exactly match the bpr fields. please see the corresponding bpr fields for the descriptions of the bpras fields. table 5-20 shows the bpra fields for bpr?s priority0. nfa1 [40:32] 0 next-free address for sub-block #1 . see nfa3 description. [45:41] reserved . multi1 [46] 1 multi free entry in sub-block #1 . see multi3 description. f1 [47] 0 free entry in sub-block #1 . see f3 description. nfa0 [56:48] 0 next-free address for sub-block #0 . see nfa3 description. [61:57] reserved . multi0 [62] 1 multi free entry in sub-block #0 . see multi3 description. f0 [63] 0 free entry in sub-block #0 . see f3 description. [71:64] reserved . table 5-19. block nfa register description (continued) field range (decimal) initial value (binary) description 7 15 23 0 39 47 55 31 63 71 priority0 v0 7 15 23 0 39 47 55 31 63 71 priority1 v1 7 15 23 0 39 47 55 31 63 71 priority2 v2 7 15 23 0 39 47 55 31 63 71 priority3 v3 figure 5-26. block priority register aliases [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 41 of 153 table 5-21 shows the bpra fields for bpr?s priority1. table 5-22 shows the bpra fields for bpr?s priority2. table 5-23 shows the bpra fields for bpr?s priority3. 5.5 multi-hit description for a search operation, multi-hit is set when there are multiple matching entries in the array (non-enhanced) or in the selecte d blocks (enhanced). for a learn operation, mult i-hit is set when there are multiple free entries in the array (non-enhanced) or in the selected blocks (enhanced). multi-hit mainta ins its value until another operation changes it. in the non-enhanced mode, the multi-hit si gnal is valid four cycles after the command is issued, regardless of the setting of t lsz and hlat. in the enhanced mode, the multi-hit signal is valid at the same time as ssv. table 5-20. block priority regist er alias for priority #0 fields field range (decimal) initial value (binary) description [23:0] reserved . priority0 [31:24] 0 priority #0 . [62:32] reserved . v0 [63] 0 v #0 . [71:64] reserved . table 5-21. block priority regist er alias for priority #1 fields field range (decimal) initial value (binary) description [15:0] reserved . priority1 [23:16] 0 priority #1 . [61:24] reserved . v1 [62] 0 v #1 . [71:63] reserved . table 5-22. block priority regist er alias for priority #2 fields field range (decimal) initial value (binary) description [7:0] reserved . priority2 [15:8] 0 priority #2 . [60:16] reserved . v2 [61] 0 v #2 . [71:62] reserved . table 5-23. block priority regist er alias for priority #3 fields field range (decimal) initial value (binary) description priority3 [7:0] 0 priority #3 . [59:8] reserved . v3 [60] 0 v #3 . [71:61] reserved . [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 42 of 153 5.6 clocks if the clk_mode pin is low, ayama 10000 receives the clk2 x and phs_l signals. it uses the phs_l signal to divide clk2x and generate an internal clock (clk [6] ), as shown in figure 5-27 . if the clk_mode pin is high, ayama 10000 receives clk1x only. ayama 10000 uses an internal phase-locked loop (pll) to lock the frequency of clk1x and generates the internal clock clk, as shown in figure 5-28 . also noted on these figures are cycles a and b. in clk2x mode, cycle a begi ns on the rising edge of clk2x, when phs_l is low, and ends on the next rising edge. cycle b begins on the rising edge of clk2x when phs_l is high, and ends on the subsequent clk2x rising edge. for clk1 x mode, the falling edge of clk1x is considered the end of cycle a, while the rising edge afte r that is considered the end of cycle b. valid data must be av ailable for the nse at the end of any cycle. note . for the purpose of showing timing diagrams, all such di agrams in this document will be shown in clk2x mode. for a timing diagram in clk1x mode, the following substitution can be made (see figure 5-29 ). notes: 6. ?clk? is an internal clock signal. 7. any reference to ?clk? cycl es means one cycle of clk. 8. only supported in non-enhanced mode. clk2x phs_l clk [7] figure 5-27. ayama 10000 clocks (clk2x and phs_l) ?cycle a end? ?cycle b end? a b input data clk1x clk [7] figure 5-28. ayama 10000 clocks (clk1x) ?cycle a end? ?cycle b end? ab input data clk2x phs_l clk1x use for clk2x mode use for clk1x mode figure 5-29. ayama 10000 clocks for all timing diagrams [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 43 of 153 5.7 phase-locked loop when the device first powers up, it takes 0.5 milliseconds (ms) after the power supplies are stable to lock the internal pll. d uring this time period, the rst_l must be held low for proper power-u p. all signals to the device in clk1x mode are sampled by a clock that is generated by multiplying clk1x by two. since t he pll has a locking range, the device will only work between the range of frequencies specified in t he timing specification wave form section of this data sheet (see section 10.0, ?ac timing parameters, waveforms and test conditions,? on page 138 ). 5.8 pipeline latency pipeline latency is used to give enough ti me for a cascaded system?s arbitration logi c to determine the dev ice that will drive the output of an operation on the sr am bus. the ayama 10000 has a default of 4 clk1x pipeline latencies but more latency can be added as necessary. the number of additional pipeline stages is set in the tlsz and hlat fields of the command register. the number of pipeline stages also controls the maximum operating speed for a single ayama 10000 nse. ta ble 5-24 lists the additional pipeline stages and the maximum operating speed. table 5-24. pipeline stages and maximum operating speed. internal register for configuration: cmd 5.9 dq bus encoding of ayama 10000 address space a set of parameters for an operation must be provided in the dq bus to the nse along with the command sent in the cmd bus. this section covers the encoding of the parameters expected in the dq bus. there are two ways of addressing an entry location or an internal register within the device: direct and indirect. the internal register s can only use direct addressing while dat a array, mask array and sram access operations can use either direct or in direct. indirect addressing allows the use of the ssr register index field as the address for a read, writ e and learn operations. indirect read operat ion on the internal registers will retur n undefined values. tlsz additional clk1x cycle latency total search clk1x cycle latency maximum operating speed (clk1x/clk2x) 00 0 4 83/166 mhz 01 1 5 100/200 mhz 10 2 6 133/266 mhz 11 invalid invalid invalid [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 44 of 153 5.9.1 addressing the data array, mask array and external sram the following table ( table 5-25 ) lists the parameters for addressing the da ta array, mask array and external sram. the address generation of the sadr bits varies depending on the operation being performed. the following table ( table 5-26 ) shows the sram address generation for the various operations. table 5-26. sram address generation table 5-25. data array, mask array an d external sram address space encoding field range (decimal) description address [n:0] address . this field contains the location of the entry to be accessed on direct addressing operations. n = 17 for cynse10512, 16 for cynse10256, 15 for CYNSE10128. note that on a burst read or write operation, the appropriate burst regi ster (wburadr or rburadr) index field is used as the address. [m] reserved . m = 18 for cynse10512, [18:17] for cynse10256, [18:16] for CYNSE10128. target [20:19] target area select . this field indicates in what context the access takes place. it is encoded as follows: 00: access the data array 01: access the mask array 10: access the external sram 11: access the internal registers (refer to section 5.9.2 ) chipid [25:21] device id . this field indicates which nse device should respond to the read or write operation. chipid value ?11111? indicates a broadcast operation. ssr [28:26] ssr index . this field selects the ssr for indirect accesses. indirect [29] indirect addressing enable . 1: indirect. when dq[30] is 0, the selected ssr register i ndex field is used to generate the address as follow: {ssr[17:3], ssr[2] | dq[2], ssr[1 ] | dq[1], ssr[0] | dq[0]}. to issue a read parity command, this bit must be se t to 1. the address of the entry location to be checked is taken from the parity control register?s adr field. no te that read parity command can be issued only on a read command. issuing an indirect write with bit[30] set to 1 will result in no- operation. 0: direct. dq[17:0] contains the address for the operation. parity [30] read parity . this bit must be set to 1 to issue a read pa rity command. it is valid only when dq[29] is also set to 1. [71:31] reserved . command sram operat ion sadr[m+8:m+6] [9] sadr[m+5:m+1] sadr[m:0] [9,10] search read cmd[8:6] id[4:0] index[m:0] learn write cmd[8:6] id[4:0] nfa/srr[m:0] [11] sram pio read read cmd[8:6] id[4:0] dq[m:0] sram pio write write cmd[8:6] id[4:0] dq[m:0] indirect read read cmd[8:6] id[4:0] ssr[m:0] | dq[2:0] [12] indirect write write cmd[8:6] id[4:0] ssr[m:0] | dq[2:0] [12] notes: 9. when multisearch feature is enabled, sadr[m+8] is not used and sadr [m] will be 0 to indicate array0 output or 1 to indicate a rray 1 output. 10. m = 17 for cynse10512; m = 16 for cynse10256; m = 15 for CYNSE10128. 11. non-enhanced mode uses nfa regist er. enhanced mode uses srr register. 12. ssr[2:0] is or-ed with dq[2:0] to generate the sadr[2:0] values. 7 15 23 0 39 47 55 31 63 71 address chipid indirect ssr parity target n = 15 for CYNSE10128 n = 16 for cynse10256 n = 17 for cynse10512 figure 5-30. data array, mask array and external sram address space encoding [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 45 of 153 5.9.2 addressing the internal registers the following table ( table 5-27 ) details the parameters expected (in dq bus) to access the internal registers of the nse. figure 5-31. internal register address space encoding 5.10 depth cascading the nse application can depth-cascade the devices to various ta ble sizes of different widths (72-bit, 144-bit, 288-bit or 576-b it). the devices perform all the necessary arbitration to decide wh ich device will drive the sram bus. some operations and features are not cascadable, which means that the operation or feature is on a device-by-device basis and t he results are not propagated to the next device. table 5-28 lists those operations and features. the followin g subsections covers the interconnects when the devices in a cascade operates in the non-enhanced mode or enhanced mode with mse set to 0 (multisearch disabled). for device interconnects when operating in enhanced m ode with multisearch enabled, please refer to figure 6-14 . 5.10.1 depth cascading up to eight devices in one block figure 5-32 shows the interconnection of up to eight devices in a casca de to form 2m 72, 1m 144, 512k 288, or 256k x 576 tables. each nse asserts the lho[1] and lho[0] signals to inform downstream devices of its result. lhi[6:0] signals for a device are connected to lho signals of the upstream devices. t he host asic must program the tlsz to 01 (binary) for each of up to eight devices in a block. only a single device drives the sram bus in any single cycle. note: 13. software solutions are possible for these case s. please refer to specific application notes. table 5-27. internal register address space encoding field range (decimal) description regsel [10:0] register address selected . this field selects which internal register to address. ta ble 5 - 3 lists the registers that are available. blknum [17:11] block number . this field selects the block within t he device that will participate in the operation. it is only used when accessing block specific internal registers (bmr, bpr, bpar, bnfa and bpra0-3). for other internal regi ster accesses, this field must be set to 0. [18] reserved . rsel [20:19] register area select . this field indicates in what cont ext the access takes place. it must be set to ?11?. chipid [25:21] device id . this field indicates which nse device should respond to the read or write operation. chipid value ?11111? indicates a broadcast operation. [28:26] reserved . indirect [29] indirect addressing enable . this bit must be cleared to 0. [71:30] reserved . table 5-28. cascadability of operations and features operations / # of devices non-enhanced enhanced mode with mse = 0 enhanced mode with mse = 1 1 2-8 9-31 1 2-8 9-31 1 2-8 9-31 multisearch command no no no no no no yes yes no learn command yes yes no yes yes no [13] yes no [13] no [13] soft priority no no no yes no [13] no [13] yes no [13] no [13] full yes yes no yes yes no yes no no multi_hit yes no no yes no no yes no no 7 15 23 0 39 47 55 31 63 71 regsel chipid indirect regsel blknum [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 46 of 153 lho[0] 6543210 lhi lho[0] 65 32 10 lhi lho[1] 6543 210 lhi lho[0] 654321 0 lhi lho[0] 654 3210 lhi lho[0] 65 4 3210 lhi lho[0] 654 32 10 lhi bho[0] 65 4 3 210 lhi lho[0] lhi lhi lhi lho[1] lho[1] lho[1] bho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[71:0] sram lho[1] lho[0] ayama 10000 #0 ayama 10000 #1 ayama 10000 #2 ayama 10000 #3 ayama 10000 #4 ayama 10000 #5 ayama 10000 #6 ayama 10000 #7 4 bho[2] bho[2] cmdv cmd[10:0] ssf, ssv figure 5-32. depth cascading in a single block [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 47 of 153 5.10.2 depth cascading up to 31 devices in 4 blocks figure 5-33 shows the cascading of up to four blocks. each bl ock except the last contains up to eight ayama 10000 devices, and the interconnection within each with the cascading of up to eigh t devices in a block was shown in the previous subsection. note . the interconnection between blocks for d epth cascading is important. for each search, a block asse rts bho[2], bho[1], and bho[0]. the bho[2:0] signals for a block are taken only from the last device in that block. for all other devices within th at block, these signals stay open. the host asic must program tlsz to 10 (binary) in each of the devices for cascading up to 31 devices (in up to four blocks). 5.10.3 depth cascading for a full signal bit[0] of each of the 72-bit entries is de signated as a special bit (1 = occupied, 0 = empty). for each learn or pio write to t he data array, each device asserts fulo[1] or fulo[0] depending on whether or not it has any empty locations within it (see figure 5-34 ). each device combines the fulo sign als from the devices above it with its own full status to generate a full signal that gives the full status of the table up to the device asserting the full signal. figure 5-34 shows the hardware connection diagram for generating the full signal that goes back to the asi c. in a depth-cascaded block of up to eight devices, the full signal from the last device should be fed ba ck to the asic controller to indicate the fu llness of the table. the full signal of the other devices should be left open. note . the learn instruction is supported for only up to eight devices, whereas full cascading is allowed only for one block in tables containing more than eigh t devices. in tables for which a learn instruction is not going to be used, the bit[0] of each 72-bit entry should always be set to 1. bho[2] block of 8 ayama 10000s block 0 bho[1] bho[0] bhi[2] bhi[1] bhi[0] bhi[2] block of 7 ayama 10000s block 3 bhi[1] bhi[0] gnd bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] gnd bhi[2] bhi[1] bhi[0] gnd block of 8 ayama 10000s block 1 block of 8 ayama 10000s block 2 dq[71:0] sram bho[2] bho[2] bho[1] bho[1] bho[0] bho[0] cmd[10:0], cmdv ssf, ssv (devices 0?7) (devices 8?15) (devices 16?23) (devices 24?30) figure 5-33. depth cascading 4 blocks [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 48 of 153 5.11 device selection in a cascaded system on a direct read operation, if the chipid fi eld matches the current device?s id[4:0], this device will respond to the read requ est. if the chipid field does not matc h, the device will not respond. no te that if the chipid does not match any device in the casca de, no read acknowledge will be generated. if the chipid is set to br oadcast (?11111?, binary), the device with the ldev bit set to 1 will respond to the read request. on an indirect read operation, if the chipid field matches the current device?s id[4:0], this device will respond to the read request. if the chipid fi eld does not match, the device will not respond. no te that if the chipid does not match any device in the cascade, no read acknowledge will be gener ated. if the chipid is set to broadcast (?11111?), each device examines its ssr register?s val and gval bits. the device with one of these bits se t responds to the read request. if none of these bits are set (this occurs when a search has not been done after a reset), no read acknowledge will be returned. on a direct write operation, if the chip id field matches the current device?s id[4:0], this device will perform the write reque st. if the chipid field does not match, the device will not respond. if the chipid is set to broadcast, all devices write to the desir ed location. fulo[0] 654 3210 fuli fulo[0] 65 4 3 2 1 0 fuli fulo[1] 65 4 3 2 1 0 fuli fulo[0] 65 4 3 2 1 0 fuli fulo[0] 6543210 fuli fulo[0] 65 4 321 0 fuli 6 5 4 3210 fuli 654 3210 fulo[0] fuli fuli fuli fulo[1] fulo[1] fulo[1] dq[71:0] fulo[1] fulo[0] vddq vddq vddq vddq vddq vddq full full full full full full full full vddq ayama 10000 ayama 10000 ayama 10000 ayama 10000 ayama 10000 ayama 10000 ayama 10000 ayama 10000 fuli fulo[0] figure 5-34. full signal generation in a cascaded table [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 49 of 153 on an indirect write operation, if the ch ipid field matches the current device, this device will perform the write request. if the chipid field does not match, the device will not respond. if the chipid is set to broadcast, different actions occur based upon the target. if the target is an internal r egister, the write request is ig nored. if the target is a data or mask array, the dev ice with the val field of the ssr register set performs the write request. if the target is extern al sram, the device with the lram field se t will drive the sram signals. 5.12 power-up sequence ayama 10000 requires that the power supplies follow a known sequence to ensure successful device power-up to set the device to its initial state. rst_l should be held low before the power supplies ramp-up and must be held low for a duration of time afterward. clock signals (clk1x/clk2x and phs_l) should start running after the power supplies become stable. all io voltages (v ddq , which includes v ddq_asic and v ddq_sram ) should only ramp up only after the core voltage (v dd ) level reaches 90% point. the following describes the proper power-up sequence required to correctly initialize the cypress network search engines before functional access to the device can begin. the follo wing steps are presented in order of priority. 1. hold rst_l and trst_l signals low and power up v dd . then power up v ddq when v dd is stable. trst_l can be tied to rst_l, tied low permanently, or driven asynchronously (more information on resett ing jtag in the jtag section of the datasheet). 2. start running clk2x/clk1x and phs_l (if applicable) after v ddq powers up. 3. hold rst_l low for at least 0.5 ms + t rstl after the clock signal is stable, then drive high. rst_l should be set high with sufficient hold time with respect to clk2x. following steps 1 through 3 will power up the device gracefully and ensure proper operation of the device. figure 5-35 illustrates the proper sequences of the power-up operation. note: the pll will lose lock if the clk2x/clk1 x or phs_l (if applicable) stop transitioning. figure 5-35. proper power-up sequence vdd vddq pll lock time, 0.5 ms t rstl clk2x phs_l trst_l/rst_l trst_l asynchronous delay trst_l trst_l can either be driven asynchronously, tied low permanently, or tied to rst_l [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 50 of 153 6.0 operations and timing diagrams a master device, such as an asic controller, issues comm ands to the ayama 10000 device using the cmd bus and cmdv signals. the following subsections descr ibe the operation of these commands. 6.1 command encoding the ayama 10000 device implements fo ur basic commands, as shown in table 6-1 . the search command is a non-blocking operation which allows another operation to be issued immediately on the following cycle. read, write and learn are blocking operations. there are also other derivative commands that the dev ice supports. the operation of basic commands as well as the derivative commands are explained in more detail in the following sections. the command code must be presented to cmd[1:0] while k eeping the cmdv signal high for two clk2x cycles (cycles a and b) when the clk_mode pin is low. in clk2x mode, the contro ller asic must align the instructions using the phs_l signal. the command code must be presented to cmd[1:0] while keeping t he cmdv signal high for one clk1x cycle when the clk_mode pin is high. in clk1x mode, cycle a ends on the falling edge of clk1x and cycle b ends on the rising edge of clk1x. valid data must be present at the edge ending an y given cycle for valid inputs. th e cmd[10:2] fiel d passes command parameters in cycles a and b. all commands must begin with cycle a operations. 6.2 command bus parameters table 6.2.1 , table 6.2.2 and table 6.2.3 list the command bus fields that cont ain the ayama 10000 command parameters and their respective cycles. 6.2.1 non-enhanced mode (emode = 0) note: 14. the nse density determines to which sadr field eadr[2:0] is mapped. in ayama10128, sadr[23:21] gets eadr[2:0]; in ayama10256 , sadr[24:22] gets eadr[2:0]; in ayama10512, sadr[25:23] gets eadr[2:0]. table 6-1. command codes command code (binary) command description 00 read reads from one of the following: data array, mask array, device registers, or external sram. read command is also used to issue read parity command. 01 write writes to one of the following: data array, mask array, device regist ers, or external sram. 10 search searches the data array for a desired pa ttern using the specified register from the gmr array and local mask associated with each data cell. 11 learn the device has internal storage for up to sixteen comparands that it can learn. the device controller can insert these entri es at the next-free address (as specified by the nfa register) using the learn instruction. cm d cycle 10 9 8 7 6 5 4 3 2 1 0 a 0 = single b 1 = burst a 0=normal 0 = single b 1=parallel 1 = burst 0=x72 0=x72 or x144 1=x144 1=x288 (first cycle) x=x288 0=x288 (last cycle) b xx a 0=x72 1=x144 learn search write read 11 10 a cmpr[3:0] cmpr[3:0] ssr[2:0] ea dr[2:0] [14] 0 xx b gmr[3] gmr[2:0] ea dr[2:0] [14] gmr[3] ea dr[2:0] [14] 0 1 0 gmr[2:0] ea dr[2:0] [14] 0 0 x x 00 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 51 of 153 6.2.2 enhanced mode (emode = 1) with multisearch disabled (mse = 0) 6.2.3 enhanced mode (emode = 1) with multisearch enabled (mse = 1) 6.3 read command in both the non-enhanced and enhanced mo de, the read command can be issued to read data from the data array, mask array, nse-associated srams or inte rnal registers. the read can be a single or burst read ( ta ble 6 -2 ). burst read can only be issued for accesses to the data or mask array locations. sram read operation is covered in section 6.7.1 to section 6.7.3 . in the enhanced mode, the read command is also us ed to issue the read parity command, wh ich is issued to perform parity check on the data and mask array entries. read is a blocking operation and must be comp leted before the next operation can be issued. table 6-2. single/burst read command parameters cmd parameter cmd[2] read command description 0 single read reads a single location of the data array, mask array, nse-associated sram or internal registers. all access information is applied on the dq bus. 1 burst read reads a block of locations from the da ta or mask array as a burst. rburreg specifies the starting address and the length of the data transfer from the data or mask array; it also auto-increments the address for each access. all other access information is applied on the dq bus. cmdcycle109876543210 a b a b 0=x72 0=x72 or x144 1=x144 1=x288/x576 (all except last cycle) x=x288/x576 0=x288/x576 (last cycle) b xx read xx eadr[2:0] [14] 000 0 0 = single 1 = burst write gmr[3] eadr[2:0] [14] gmr[2:0] 0=normal 1=parallel 11 search a gmr[3] eadr[2:0] [14] 0=cmpr 1=dq 0=data 1=mask learn cmpr[3:0] 01 0 gmr[2:0] 10 0 = single 1 = burst cmpr[3:0] ssr[2:0] 0 a 00 b eadr[2:0] [14] 00: x72; 01: x144; 1x:x288/x576 (all except last cycle); 0x:x288/x576 (last cycle) cm d cycle 10 9 8 7 6 5 4 3 2 1 0 a 0 b a 0 b 0=x72 0=x72 or x144 1=x144 1=x288/x576 (all except last cycles) x=x288/x576 0=x288/x576 (last cycle) b xx eadr[1:0] [14] eadr[1:0] [14] eadr[1:0] [14] eadr[1:0] [14] ssr[2:0] 0=single-search 1=multi-search 1 b 00 0 0 00: x72; 01: x144; 1x:x288/x576 (all except last cycle); 0x:x288/x576 (last cycle) 0=data 1=mask 0=cmpr 1=dq learn a cmpr[3:0] 1 1 0 search a gmr[3] gmr[2:0] 10 write cmpr[3:0] gmr[3] gmr[2:0] 00 0 0 = single 1 = burst 0 = single 1 = burst 0=normal 1=parallel 0 0 read xx [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 52 of 153 6.3.1 single read a single read operation lasts six cycles (clk1x) with the data driven out by the nse on cycle 5 as illustrated in figure 6-1 . read operation sequence: ? cycle 1 : the host asic applies the read instruction on cmd[1:0] (cmd[2] = 0) using cmdv = 1, and the dq bus supplies the address. the host asic selects the ayama 10000 device for which id[4:0] matches the dq[ 25:21] lines. if dq[25:21] = 11111, the host asic selects the ayama 10000 with the ldev bit set. the host asic also s upplies sadr[25:23] for cynse10512, sadr[24:22] for cynse10256, sadr[23:21] for CYNSE10128 on cmd[8:6] in cycle a of the read instruction if the read is directed to the external sram. ? cycle 2 : the host asic floats dq[71:0] to a three-state condition. ? cycle 3 : the host asic keeps dq[71:0] in a three-state condition. ? cycle 4 : the selected device starts to drive the dq[71:0] bus and drives the ack signal from z to low. ? cycle 5 : the selected device drives the read data from the addre ssed location on the dq[71:0] bus, and drives the ack signal high. ? cycle 6 : the selected device floats the dq[71:0] to a th ree-state condition and drives the ack signal low. at the termination of cycle 6, the selected device releases the ack line to a three-st ate condition. the read instruction is co mplete and the next operation can begin. 6.3.2 burst read the burst read operation lasts 4 + 2n clk1x cycles, where n is the number of the burst length as specified by the blen field of the rburreg. the blen field is automatically decremented after each read of the burst, so the register must be reinitialized before another burst read is iss ued. instead of the address provided by the user , the address in the index field of the rburreg is used and incremented each cycle. figure 6-2 illustrates the timing diagram for the burst read of the data or mask array. cycle cycle cycle cycle cycle cycle read address 0data 1 2 345 6 clk2x cmdv cmd[1:0] ack dq cmd[10:2] a b phs_l figure 6-1. single-location read cycle timing [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 53 of 153 burst read operation sequence: ? cycle 1 : the host asic applies the read instruction on cmd[1:0] (cmd[2] = 1) using cmdv = 1, and the address supplied on the dq bus. the host asic selects the ayama 10000 device where id[4:0] matche s the dq[25:21] lines. if dq[25:21] = 11111, the host asic selects the ayama 1 0000 device with the ldev bit set. ? cycle 2 : the host asic floats dq[71:0] to a three-state condition. ? cycle 3 : the host asic keeps dq[71:0] in a three-state condition. ? cycle 4 : the selected device starts to drive the dq[71: 0] bus and drives ack and eot from z to low. ? cycle 5 : the selected device drives the read data from the addre ss location on the dq[71:0] bus and drives the ack signal high. cycles 4 and 5 repeat for each additional access until all the accesses specified in the blen field of rburreg are complete. on the last data transfer, the ayam a 10000 drives the eot signal high. cycle (4 + 2n) : the selected device drives the dq[71:0] to a thre e-state condition, and driv es ack and eot signals low. at the termination of cycle (4 + 2n), the selected device float s ack and eot to a three-state condition. the burst read operati on is complete and the next operation can begin. 6.3.3 read parity data output of the read parity command should be ignored. read parity is a blocking operation only on the cycles as the normal read operation even though the parity status signal (parerr) is valid tlsz cycles later. figure shows an example of the parerr update timing diagram with tlsz set to ?10? (two additional cycles of latency) to a total of eight cycles (six read cycl es plus two tlsz cycles). 6.4 write command the write command can be issued to write to the data array, mask array, nse-associated srams or internal registers. the write can be a single or burst write ( ta ble 6-3 ). burst write can only be issued for accesses to the data or mask array locations. sram write operation is covered in section 6.7.4 to section 6.7.6 . the write command is also used to issue the parallel write command. note that when parity feature is enabled masks will be ignored and all bits will be written as presented in the dq bus. cmdv cmd[1:0] ack eot dq 0 0 data1 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cycle 11 cycle 12 data0 data2 0 data3 0 phs_l cmd[10:2] address a b read clk2x figure 6-2. burst read of the data and mask arrays (blen = 4) [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 54 of 153 write is a blocking operation and must be co mpleted before the next operation can be issued. 6.4.1 single write a single write operation lasts 3 cycl es (clk1x) as illustrated in figure 6-3 . write operation sequence: ? cycle 1a: the host asic applies the write instruction to cmd[1:0] (cmd[2] = 0) using cmdv = 1, and the target address supplied on the dq bus. the host asic also supplies the gmr in dex to mask the write to the data or mask array location on {cmd[10], cmd[5:3]}. for sram writes, the host asic mu st supply the sadr[ 25:23] for cynse105 12, sadr[24:22] for cynse10256, sadr[23:21] for cynse10 128 on cmd[8:6]. the host asic sets cmd[9] to 0 for a normal write. ? cycle 1b: the host asic continues to apply the write instruction to cmd[1:0] (cmd[2] = 0) using cmdv = 1, and the address supplied on the dq bus. the host asic continues to supply the gmr index to mask the write to the data or mask array locations in {cmd[10], cmd[5:3] }. the host asic selects the device where id[4:0 ] matches the dq[25:21] lines, or it selects all the devices when dq[25:21] = 11111. ? cycle 2: the host asic drives dq[71:0] with the dat a to be written to the data array, mask array, or register location of the selected device. ? cycle 3: idle cycle. dq bus should be driven to 0. at the termination of cycle 3, another operation can begin. 6.4.2 burst write the burst write operation lasts 2 + n clk1x cycles, where n is the number of the burst length as specified by the blen field of the wburreg. the blen field is aut omatically decremented after each write of the burst, so the register must be re-initialized before another burst write is issued. instead of the address provided by the user, the address in the index field of the wburreg is used and incremented each cycle. table 6-3. single/burst write command parameters cmd parameter cmd[2] write command description 0 single write writes a single location of the data arra y, mask array, nse-associ ated sram or internal registers. all access informat ion is applied on the dq bus. 1 burst write writes a block of loca tions to the data or mask array as a burst. wburreg specifies the starting address and the length of the data tr ansfer from the data or mask array; it also auto-increments the address for each access. all other access information is applied on the dq bus. cycle 2 cycle 3 write address data cmdv cmd[1:0] dq 0 cycle 1 cycle 0 cycle 4 cmd[10:2] b phs_l a clk2x figure 6-3. single write cycle timing [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 55 of 153 figure 6-4 illustrates the timing diagram for the burst write to the data or mask array. burst write operation sequence: ? cycle 1a : the host asic applies the write instru ction to cmd[1:0] (cmd[2] = 1) usi ng cmdv = 1, and the address supplied on the dq bus. the host asic also supplies the gmr index to ma sk the write to the data or mask array locations in {cmd[10], cmd[5:3]}. the host asic sets cm d[9] to 0 for the normal write. ? cycle 1b : the host asic continues to apply the write instruction on cmd[1:0] (cmd[2] = 1) using cmdv = 1, and the address supplied on the dq bus. the host asic continues to supply the gmr index to mask the write to the data or mask array locations in {cmd[10], cmd[5:3]}. the host asic selects the de vice for which id[4:0 ] matches the dq[25:21] lines. it selects all devices when dq[25:21] = 11111. ? cycle 2 : the host asic drives the dq[71:0] with th e data to be written to the data or mask array location of the selected device. the ayama 10000 device writes the data from the dq[71:0] bus only to the subfield with the corresponding mask bit set to 1 in the gmr that is specif ied by the index {cmd[10],c md[5:3]} supplied in cycle 1. ? cycles 3 to n + 1 : the host asic drives the dq[71:0] wit h the data to be written to the next data or mask array location of the selected device (addressed by the auto-inc rement adr field of the wburreg register). the ayama 10000 device writes the data on the dq[71:0] bus only to t he subfield that has the corresponding mask bit set to 1 in the gmr specified by the in dex supplied in cycle 1 {cmd[10] ,cmd[5:3]}. the ayama 10000 devic e drives the eot signal low from cycle 3 to cycle n; the ayama 10000 device drives the eot signal high in cycle n + 1 (n is specified in the blen field of the wburreg). ? cycle n + 2: the ayama 10000 device drives the eot signal low. at the termination of cycle n + 2, the ayam a 10000 device floats the eot signal to a three-state operation and the next instruc tion can be issued. 6.4.3 parallel write in order to write the data or mask array faster for initializatio n, testing, or diagnostics, the user can issue a parallel writ e command. parallel write allows the user to specify one address and write multiple locations in the core with the same data. parallel wri te only works with direct addressing. if indirect addressing is used, the operation will result in no -operation. parallel write ca n also be done in burst operation. in non-enhanced mode, address bits dq[10: 1] specify which location to perform para llel write. dq[17:11] defines a set of partitions, all of which write two x72 entr ies (dq[0] is ignored). for ayama 10512, this corresponds to 64 parallel locations ( 32 8kx72 partitions, 2 loca tions per partition). in enhanced mode , address bits dq[10:0] specify the location within a block. para llel write only occurs on those blocks which match the mini-key(s) selected by the gmr field. for ayama 105 12, this corresponds to 128 parallel locations (128 blocks, 1 location per block). 1 data0 data1 data2 0 data3 write address cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle cmd[1:0] dq clk2x eot cmd[10:2] a b phs_l cmdv figure 6-4. burst write of the data and mask arrays (blen = 4) dq should be driven to zero in this cycle [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 56 of 153 6.5 search command one of the key parameters that controls search operation is tlsz (statically programmed in command register). tlsz controls the maximum number of devices that can be cascaded and the latency of search instruction, as shown in table 6-4 . the following is a list of search operations described in the data sheet: ? mixed-size single search for a single device on tabl es configured with different widths (tlsz[1:0] = 01) ? mixed-size multisearch for a single device on tabl es configured with differen t widths (tlsz[1:0] = 01) ? 72-bit single search for single device or ca scade up to eight devices (tlsz[1:0] = 01) ? 72-bit multisearch for single device or cascade up to eight devices (tlsz[1:0] = 01) ? 144-bit single search for cascade up to 31 devices (tlsz[1:0] = 10) ? 576-bit single search for single device or cascade up to eight devices (tlsz[1:0] = 01) ? 576-bit multisearch for single device or cascade up to eight devices (tlsz[1:0] = 01) ? mixed-size single search for cascade up to 31 devices on tables configured with different widths (tlsz[1:0] = 10) ? mixed-size multisearch for cascade up to eight devices on tables configured with different widths (tlsz[1:0] = 01). 6.5.1 mixed-size single searches with one devi ce on tables configured with different widths this subsection covers single-searches with a single device c onfigured with tables of different widths (72, 144, 288). figure 6-5 shows three sequential searches: first, a 72-bit search on a 7 2-configured table; a 144-bit search on a 144-configured table; and a 288-bit search on a 288-configured table that each results in a hit. figure 6-6 shows the sample table. note : if the mixed-size tables include a 576-bit table, then the device can only operate in the enhanced mode, as the maximum table width allowed in the non-enhanced mode is 288 bits. one way to create multiple tables of different widths in an nse is by having table designation bits. it is assumed that bits [71:70] for each entry will be assigned such table designation bits. dq[71:70] wi ll be 00 in each of the two a and b cycles of the 72-bit search (search1). dq[71:70] is 01 in each of the a and b cycles of the 144-bi t search (search2). dq[71:70] is 10 in each of the a, b, c, and d cycles of the 288-bit search (search3). table 6-4. tlsz[1:0] description tlsz[1:0] max. number of devices allowed in a cascaded nses search latencies (clk1x cycles) max. table size (wit h max. number of devices 00 not supported not applicable not applicable 01 8 5 n x 72 n/2 x 144 n/4 x 288 n/8 x 576 n = 2048k for cynse10512, 1024k for cynse10256, 512k for CYNSE10128 10 31 (in single-search mode, 8 in multisearch mode) 6n x 72 n/2 x 144 n/4 x 288 n/8 x 576 n = 7936k for cynse10512, 3968k for cynse10256, 1984k for CYNSE10128 11 reserved reserved reserved [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 57 of 153 tlsz = 01 (binary), lram = 1 (binary), ldev = 1 (binary) for this particular example. the following is the sequence of operation for a single search command (also refer to subsection 6.2, ?command bus param- eters,? on page 50 ). ? cycle a : ? command bus : the host asic drives cmdv high and applies se arch command cmd[1:0] = ?10?. the cmd[2] and cmd[9] signals must be driven to logic 0 for the 72-bit s earch, but for 144-bit search, cm d[9] = 1 and cmd [2] = 0. for 288-bit search, cmd[9] is don?t care, whereas cmd[2] = 1 for the first ?a? cycle and 0 for the last ?a? cycle. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair for us e in this search operation. cmd[8:6] signals must be driven with the same bits that will be driven on sadr[25:23] for cynse10512, sadr[24:22] for cynse10256, sadr[23:21] for cy nse10128 if it has a hit. ? dq bus : at the same time in cycle a, dq[71:0] must be driv en with the 72-bit data to be compared. cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 hlat = 001 (binary), tlsz = 00 (binary), lram = 1 (binary), ldev = 1 (binary). m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 phs_l sadr[ m :0] ssf ssv ale_l search1 search2 addr 10 10 search1 search3 a b a b a b a b 0 1 0 1 0 1 x y1 y2 z1 z2 z3 z4 dq d1 d3 addr search2 10 d2 1 0 0 1 0 1 72 hit 144 hit search3 288 hit addr figure 6-5. timing diagram for mixed single search (one device) cmd[2] the last a-cycle cmpr[2] on b-cycles logic 0 for a-cycles for x72 and x144 logic 0 on 1st x288 a-cycle logic 1 on the 1 0 1 1 x y z [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 58 of 153 ? cycle b : ? command bus : the host asic continues to drive cmdv high and to apply search command cm d[1:0] = ?10?. cmd[5:2] must now be driven by the index of the comparand register pa ir for storing the search key presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and hit flag (see page 27 for a description of ssr[0:7]). cmd[10:9] are don?t cares for this cycle. ? dq bus : the dq[71:0] continues to carry the search key to be compared. note . for 72-bit searches, the host asic must supply the same 72-bit data on dq[71:0] during both cycles a and b. also, the even and odd pairs of gmrs selected for the comparison must be programmed with the same value. for 144-bit, 288-bit or 576- bit searches, each 72-bit presented on each cycle a and b will to gether form the 144-bit or 28 8-bit or 576-bit search key respectively. when an n-bit search key, k, is presented on the dq bus, the entire table of n-bit ent ries is compared to the search key using the gmr and local mask bits. the gmr is selected by the gmr i ndex in the command?s cycle a. k is also stored in both even and odd comparand register pairs (selected by the comparand re gister index in command cycle b). k is compared with each entry in the table, starting at location 0. a matching entry that sa tisfies the soft priority and mini -key scheme (for enhanced mode) will be the winning entry, and its location address l will be driv en as part of the sram addr ess on the sadr[n:0] lines (see section 6.7, ?sram pio access,? on page 121 ), n = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128. the latency of the search from command to sram access cycle is 5 for up to eight devices in the t able (tlsz[1:0] = 01). ssv and ssf also shift further to the right for different values of hlat, as specified in table 6-5 . figure 6-6 shows an example of multiple table configuration with a cynse10512 device. referring to figure 6-6 , if the cynse10512 device is used in the non-en hanced mode, the cfg fiel d in the configuration register should be configured to ?1010101010101010010101010101010100000000000000000000000000000000? in order to have three individual tables within a device. if the device is used in the enhanced mode, the nes field in the block mini-key register (bmr) should be configured as follows: ? for the first 64 blocks in the data array, nes = 00 for 72-bit table width. ? for the next 32 blocks, nes = 01 for 144-bit table width. ? for the final 32 blocks, nes = 10 for 288-bit table width. 6.5.2 mixed-size multi searches with one devi ce on tables configured with different widths the multiple search operates the search commands in parallel on the upper half (array 0) and lower half (array 1) of the data array in the device. the results from the tw o parallel searches are then driven on the sram bus at twice that rate relative to single-search. this subsection covers multi searches with a si ngle device configured with tables of different widths (72, 144 , 288) in each of the two arrays. figure 6-7 shows three sequential searches: first, a 72-bit search on a 72-configured table; a 144-bit search on a 144-configured table; and a 288-bit search on a 288-configured table. note : multisearch is only available in the en hanced mode, not in the non-enhanced mode. figure 6-8 shows the sample table. one way to create multiple tables of different widths in an nse is by having table designation bits. it is assumed that bits [71:70] for each entry will be assigned such table designation bits. dq[71:70] wi ll be 00 in each of the two a and b cycles of the 72-bit multisearch (m-search1). dq[71:70] is 01 in each of the a and b cycles of the 144- bit multisearch (m-search2). dq[71:70] is 10 in each of the a, b, c, and d cycles of the 288-bit multisearch (m-search3). table 6-5. shift of ssf and ssv from sadr hlat (binary) number of clk c ycles hlat number of clk cycles 000 0 100 4 001 1 101 5 010 2 110 6 011 3 111 7 16k 128k 72 32k 144 288 figure 6-6. multiwidth configurations using cynse10512 as an example [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 59 of 153 the mse bit in the command register must be set high to enabl e the multisearch feature. th e same with the enhanced mode (emode) bit. tlsz = 01 (binary), lram = 1 (binary), ldev = 1 (binary) for a single-d evice configuration. hlat = 000 (binary) for this example. the following is the sequence of operation for a single search command (also refer to subsection 6.2, ?command bus parameters,? on page 50 ). ? cycle a : ? command bus : the host asic drives cmdv high and applies se arch command cmd[1:0] = ?10?. the cmd[2] and cmd[9] signals must be driven to logic 0 for the 72-bit s earch, but for 144-bit search, cm d[9] = 1 and cmd [2] = 0. for 288-bit search, cmd[9] is don?t care, whereas cmd[2] = 1 for the first ?a? cycle and 0 for the last ?a? cycle. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair for us e in this search operation. cmd[7:6] signals must be driven with the same bits that will be driven on sadr[24:23] for cynse10512, sadr[23:22] for cynse10256, sadr[22:21] for CYNSE10128 by this device if it has a hit. cmd[8] must be driven high for multisearch operation. cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 hlat = 000 (binary), tlsz = 00 (binary), lram = 1 (binary), ldev = 1 (binary). phs_l sadr[ m :0] ssf ssv ale_l miss in array 1 10 10 m-search1 m-search3 a b a b a b a b 1 1 0 0 w y1 y2 z1 z2 z3 z4 dq d1 d3 addr m-search2 10 d2 1 72 hit 144 hit 288 miss figure 6-7. timing diagram for mixed multisearch (one device) cmd[2] the last a-cycle cmpr[2] on b-cycles logic 0 for a-cycles for x72 and x144 logic 0 on 1st x288 a-cycle logic 1 on the x d4 addr w addr x addr y z miss in array 0 1 1 0 0 1 1 0 1 1 0 0 in array 0 72 hit in array 1 in array 0 144 miss in array 1 in array 0 288 hit in array 1 m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 60 of 153 ? dq bus : at the same time in cycle a, dq[71:0] must be driv en with the 72-bit data to be compared. ? cycle b : ? command bus : the host asic continues to drive cmdv high and to apply search command cm d[1:0] = ?10?. cmd[5:2] must now be driven by the index of the comparand register pa ir for storing the search key presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and hit flag (see page 27 for a description of ssr[0:7]). cmd[10:9] are don?t cares for this cycle. ? dq bus : the dq[71:0] continues to carry the search key to be compared. note . for 72-bit searches, the host asic can su pply different 72-bit data on dq[71:0] during both cycl es a and b to be compared with the tables in array 0 and 1 of the data array. the even and odd pairs of gmrs selected for the comparison need not be programmed with the same value. for 144-bit, 288-bit or 576- bit searches, each 72-bit presented on each cycle a and b will together form the 144-bit or 288- bit or 576-bit search key respec tively. these search keys are compared to both array 0 and 1 during cycles a and b. when an n-bit search key, k, is presented on the dq bus, both a rrays of n-bit entries are compared to the search key using the gmr and local mask bits. the gmr is selected by the gmr inde x in the command?s cycle a. k is also stored in both even and odd comparand register pairs (selected by the comparand regist er index in command cycle b). k is compared with each entry in the table, starting at location 0. a matc hing entry from each array that satisfies the soft priority and mini-key scheme will b e the winning entries, and their location addresses la and lb will be dr iven as part of the sram a ddress on the sadr[n:0] lines (see section 6.7, ?sram pio access,? on page 121 ), n = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128. the latency of the search from command to sram access cycle is 5 for a single device (or up to ei ght devices) configuration in the table (tlsz[1:0] = 01). ssv and ssf al so shift further to the ri ght for different values of hlat, as specified in ta ble 6-5 . figure 6-8 shows a multiwidth configuration when multisearch is enabled using cynse10512 as an example. the nes field in the block mini-key register (bmr) should be configured as follows: ? for the first 32 blocks in the data array, n es = 00 (binary) for 72-bit table width. for the next 16 blocks, nes = 01 (binary) for 144-bit table width. for the following 16 blocks, nes = 10 (binar y) for 288-bit table width. these will configure the tables in array 0. ? setting nes = 00 (binary) for the next 32 blocks will configure those blocks to be 72-bit table in array 1. setting nes = 01 (binary) for the next 16 blocks will config ure those blocks to be 144-bit table. se tting the final 16 bloc ks? nes field will co nfigure those blocks to be 288-bit table. 6.5.3 72-bit single search for 1 device or cascade up to eight devices the hardware diagram of the se arch subsystem of up to eight devices is shown in figure 6-9 . the multisearch mode (mse) bit in the command register must be set low to perform single-s earch. the following are the rest of the parameters programmed into the eight devices. ? in non-enhanced mode, first seven devices (devices 0?6) must rese t all bits of the cfg field in configuration register to zero es. in enhanced mode, these devices should have the nes field of each block within a device configured to 00 for 72-bit table width. tlsz = 01 (binary), hlat = 010 (binary), lram = 0 (binary), and ldev = 0 (binary) for both modes. ? in non-enhanced mode, the eighth device (d evice 7) should still reset all bits of th e cfg field in configuration register to zeroes. in enhanced mode, nes should still be 00 (binary). but tl sz = 01 (binary), hlat = 010 (binary), lram = 1 (binary), and ldev = 1 (binary) for the last device note : the device receiving all the lho signals from the other devices is the last device. for a single-device configuration, the para meters are the same as device 7. bhi[2:0] and lhi[6:0] should be tied to ground. 8k 64k 72 16k 144 288 upper half lower half 8k 64k 72 16k 144 288 (array 0) (array 1) figure 6-8. multiwidth configurations using cynse10512 as an example [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 61 of 153 the following three figures show the response of three of the ei ght devices having a hit at different time according to a hit/m iss assumption shown below in table 6-6 . for these timing diagrams, four 72-bit searches are performed sequentially. figure 6-10 shows the timing diagram for a search command in the 72 -bit-configured table of eight devices for device number 0. figure 6- 11 and figure 6-12 shows the same for device number 1 and number 7 (the last device in this specific table) respectively. note : all the shared signals showing tri-stated co ndition (?z?) indicate that, that partic ular device is not driving the shared sig nals. the shared signals are not three-stated in a real li fe because other devices will be driving them. table 6-6. hit/miss assumptions search number 1 2 3 4 device 0 hit miss hit miss device 1 miss hit hit miss devices 2?6 miss miss miss miss device 7 miss miss hit hit lho[0] 6543210 lhi lho[0] 65 32 10 lhi lho[1] 6543 210 lhi lho[0] 654321 0 lhi lho[0] 654 3210 lhi lho[0] 65 4 3210 lhi lho[0] 654 32 10 lhi bho[0] 65 4 3210 lhi lho[0] lhi lhi lhi lho[1] lho[1] lho[1] bho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[71:0] sram lho[1] lho[0] ayama 10000 #0 ayama 10000 #1 ayama 10000 #2 ayama 10000 #3 ayama 10000 #4 ayama 10000 #5 ayama 10000 #7 4 bho[2] bho[2] cmdv cmd[10:0] ssf, ssv ayama 10000 #6 figure 6-9. hardware diagram for a table with eight devices [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 62 of 153 search2 search4 w x y z 10 10 10 10 a b a b a b a b cycle clk2x cmdv cmd[1:0] dq ce_l oe_l (this cmd[10:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg[n:0] are all zeroes for non-enhanced mode, n = 63 for cynse10512, 3 1 for cynse10256, 15 for CYNSE10128 nes = 00 (binary) in each block for enhanced mode. hlat = 010 (binary), tlsz = 01 (binary), lram = 0 (binary), ldev = 0 (binary). note: |(lhi[6:0]) stands for the bool ean ?or? of the ent ire bus lhi[6:0]. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[m:0] ssf ssv ale_l search1 search3 search4 search1 search3 addr addr z z z z z z z z z z z z z z 0 0 1 0 0 1 1 1 z z device is the global winner.) (this device is the global winner.) |(lhi[6:0]) 0 this device.) (miss on this device.) lho[1:0] search2 (miss on figure 6-10. timing diagram for 72-bit search device number 0 w y m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 z 1 1 z z [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 63 of 153 cfg[n:0] are all zeroes for non-e nhanced mode, n = 63 for cynse10512, 31 for cynse10256, 15 for CYNSE10128. nes = 00 (binary) in each block for enhanced mode. hlat = 010 (binary), tlsz = 01 (binary), lram = 0 (binary), ldev = 0 (binary). note: |(lhi[6:0]) stands for the bool ean ?or? of the entire bus lhi[6:0]. note: each bit in lho[1:0] is the same logical signal. search2 search4 w x y z 10 10 10 10 a b a b a b a b cycle clk2x cmdv cmd[1:0] dq ce_l oe_l (miss cmd[10:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[m:0] ssf ssv ale_l search1 search2 search3 search4 search1 search3 addr z z z 1 z (local winner but not global winner) (miss on this device) |(lhi[6:0]) lho[1:0] z 0 z z 0 z z 1 z on this device) (this device winner) is global figure 6-11. timing diagram for 72-bit search device number 1 0 0 0 0 0 1 1 1 x m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 z 1 z [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 64 of 153 the following is the sequence of operation for a single 72-bit search command (also refer to subsection 6.2, ?command bus parameters,? on page 50 ). ? cycle a : ? command bus : the host asic drives cmdv high and applies se arch command cmd[1:0] = ?10?. the cmd[2] and cmd[9] signals must be driven to logic 0 for this 72-bit sear ch. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair for use in this search operation. cmd[8:6] si gnals must be driven with the same bits that will be driven on sadr[25:23] for cynse10512, sadr [24:22] for cynse10256, sadr[23 :21] for CYNSE10128 by this device if it has a hit. ? dq bus : at the same time in cycle a, dq[71:0] must be driv en with the 72-bit data to be compared. ? cycle b : ? command bus : the host asic continues to drive cmdv high and to apply search command cm d[1:0] = ?10?. cmd[5:2] must now be driven by the index of the comparand register pair for storing the two 72-bit word presented on the dq bus during cycles a and b. cmd[ 8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and hit flag (see page 27 for a descripti on of ssr[0:7]). cmd[10:9] ar e don?t cares for this cycle. ? dq bus : the dq[71:0] continues to carry the 72-bit data to be compared. note . for 72-bit searches, the host asic must supply the same 72-bit data on dq[71:0] during both cycles a and b. also, the even and odd pairs of gmrs selected for the co mparison must be programmed with the same value. cfg are all zeroes for non-enhanced mode, nes = 00 (binary) in each block for enhanced mode. hlat = 010 (binary), tlsz = 01 (binary), lram = 1 (binary), ldev = 1 (binary). note: |(lhi[6:0]) stands for the bool ean ?or? of the ent ire bus lhi[6:0]. note: each bit in lho[1:0] is the same logical signal. search2 search4 w x y z 10 10 10 10 a b a b a b a b addr z 1 1 0 0 0 0 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l (miss on cmd[10:2] 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[m:0] ssf ssv search1 search2 search3 search1 search3 0 (local winner but not global winner) |(lhi[6:0]) lho[1:0] this device) (miss on this device) 0 z 0 0z 0 ale_l we_l 1z 1 0 z 1 0 search4 (global winner) figure 6-12. timing diagram for 72-bit search device number 7 (last device) z m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 0 z 1 0 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 65 of 153 the logical 72-bit search operation is shown in figure 6-13 . the entire table of 72-bit entries (eight devices) is compared to a 72-bit word k (presented on the dq bus in both cycles a and b of the command) using the gmr and local mask bits. the effective gmr is the 72-bit word specified by the ident ical value in both even and odd gmr pairs, in each of the eight devices, and selec ted by the gmr index in the command?s cycle a. the 72-bit word k (present ed on the dq bus in both cycle s a and b of the command) is also stored in both even and odd comparand register pairs (selected by the comparand register index in command cycle b) in each of the eight devices. in the 72 configuration, only the even comparand register can subsequently be used by the learn command in one of the devices (the first non-full device only). the word k (presented on the dq bus in both cycles a and b of the command) is compared with each entry in the table, starting at location 0. a matc hing entry that sati sfies the soft priorit y and mini-key scheme (for enhanced mode) will be the winning entry, and its location address l will be driven as part of the sram address on the sadr[n:0] lines (see section 6.7, ?sram pio access,? on page 121 ), n = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128. the global winning device will drive the bus in a specific cycle. on a global miss cycle, the device with lram = 1 (default driving device for the sram bus) and ldev = 1 (default driving device for ssf and ssv signals) will be the default driver for such missed cycles. the search command is a pipelined operation and executes a s earch at half the rate of t he frequency of clk2x for 72-bit searches in 72-configured tables. the latency of sadr, ce_l , ale_l, we_l, ssv, and ssf from the 72-bit search command cycle (two clk2x cycles) is shown in ta ble 6-4 . the latency of the search from command to sram access cycle is 5 for up to eight devices in the table (tlsz = 01). ssv and ssf also shift further to the right for di fferent values of hlat, as specified in table 6-5 . 6.5.4 72-bit multisearch for one device or cascade up to eight devices the multiple search operates the search commands in parallel on the upper half (array 0) and lower half (array 1) of the data array in the device. the results from the tw o parallel searches are then driven on the sram bus at twice that rate relative to single-search. the hardware diagram of the search subsystem of up to eight devices is shown in figure 6-14 below. note : ? multisearch feature is only available in t he enhanced mode, not in the non-enhanced mode. ? comparing the hardware diagrams shown in figure 6-9 and figure 6-14 , enabling multisearch does not mean that a board layout change is required. the lho_1_l and lhi_1_l share the sa me pin with the full in and full out signals, which are not shown in figure 6-9 . cascading multiple devices togethe r still allow the user to configur e the devices through software to perform single-search or multisearch operations without any board change. ? the device receiving all the lho signals fr om the other devices is the last device. ? all the shared signals showing three-stated condition (?z?) indica te that, that particular device is not driving the shared si gnals. the shared signals are not three-stated in a real life because other devices will be driving them. 71 0 location 0 1 2 3 n (72-bit configuration) address k gmr comparand register (odd) comparand register (even) k k 71 0 71 0 (first matching entry) l must be same in each of the eight devices will be same in each of the eight devices figure 6-13. 72 table with eight devices n = 2097151 for cynse10512 1048575 for cynse10256 524287 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 66 of 153 notes : ? in multisearchmode, there is a separate set of the lho and lhi signals corresponding to memory array 0 and array 1. lho_0[1:0] and lhi_0[ 6:0] corresponds to array 0 whereas lho_1_l[1:0] and lhi_1_l[6:0] corre sponds to array 1. the latter share the same pins as fulo[1:0] and fuli[6:0] respectively. ? both lho_0[1] and lho_0[ 0] are exact same signals so that the loads can be shared by two outputs. the same is true for lho_1_l[1] and lho_1_l[0]. ? unused lhi_0 signals should be tied to ground whereas unused lhi_1_l signals should be tied to v ddq_asic , which is either 1.8v or 2.5v only. lho_0[0] 6 543 21 0 lhi_0 lho_0[0] lhi_0 lho_0[1] lhi_0 lho_0[0] lhi_0 lho_0[0] lhi_0 lho_0[0] lho_0[0] bho[0] lhi_0 lho[0] lhi_0 lhi_0 lho_0[1] lho_0[1] lho_0[1] bho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[71:0] sram lho_0[1] lho_0[0] ayama 10000 #0 ayama 10000 #1 ayama 10000 #2 ayama 10000 #3 ayama 10000 #4 ayama 10000 #5 ayama 10000 #7 bho[2] bho[2] cmdv cmd[10:0] ssf, ssv ayama 10000 #6 6 543 21 0 6 543 21 0 6 543 21 0 6 543 21 0 6 543 21 0 6 543 21 0 6 543 21 0 lho_1_l[0] 6 543 21 0 lhi_1_l lho_1_l[0] lhi_1_l lho_1_l[1] lhi_1_l lho_1_l[0] lhi_1_l lho_1_l[0] lhi_1_l lho_1_l[0] lho_1_l[0] lhi_1_l lho_1_l[0] lhi_1_l lhi_1_l lho_1_l[1] lho_1_l[1] lho_1_l[1] 6 543 21 0 6 543 21 0 6 543 21 0 6 543 21 0 6 543 21 0 6 543 21 0 6 543 21 0 lho_1_l[1] lho_1_l[0] figure 6-14. hardware diagram for a table with eight devices for multisearch v ddq_asic v ddq_asic v ddq_asic v ddq_asic v ddq_asic v ddq_asic v ddq_asic [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 67 of 153 ? lhi_1_l signals are active low while lhi_0 are active high. the multisearch enable (mse) bit in the command register must be set high when the command register is programmed. the same with the enhanced mode (emode) bi t. the following are the rest of the parame ters programmed into the eight devices. ? first seven devices (devices 0?6): nes = 00 (binary) for each block in each device, tlsz = 01 (binary), hlat = 001 (binary), lram = 0 (binary), and ldev = 0 (binary). ? eighth device (device 7): nes = 00 (binary) for each block in each device, tlsz = 01 (binary), hlat = 001 (binary), lram = 1 (binary), and ldev = 1 (binary). for a single-device configuration, the para meters are the same as device 7. bhi[2:0] and lhi[6:0] should be tied to ground. the following three figures show the response of 3 of the 8 de vices having a hit at different time according to a hit/miss assu mption shown below in ta ble 6-7 . for these timing diagrams, five 72-bit searches are performed sequentially. figure 6-15 shows the timing diagram for a search command in the 72-bit-conf igured table of eight devices for device number 0. figure 6-16 and figure 6-17 shows the same for device number 1 and number 7 (the last device in this spec ific table) respectively. table 6-7. hit/miss assumption for multisearch mode search #12345 device 0 hit miss hit miss hit miss miss hit hit hit device 1 miss hit hit miss hit hit miss miss miss miss devices 2?6 miss miss miss miss miss miss miss miss miss miss device 7 miss miss hit hit miss hit hit miss miss miss [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 68 of 153 notes: ? each ?cycle? consists of 2 clk2x cycle s, which is effect ively one clk1x cycle. ? the latency of ssv and ssf specifi ed by hlat refers to clk1x cycles. ? lho_0[1:0] will be va lid 4 (clk1x) cycles after the search parameter is sa mpled, regardless of the num ber of searches entered; e.g., the search parame ter a entered on dq bus is sampled at cycl e 1, lho_0[1:0] will be available at cycle 5. ? for tlsz[1:0] = 01, all signals on sram interface will be driv en 5 (clk1x) cycles after the search parameter is sampled, regardless of the number of searches; e.g., the search parameter a sampled on cycle 1 is a hit, thus the address value sent to sadr bus and the rest of the sram c ontrol signals will be driven at cycle 6. m-search2 m-search4 10 10 10 10 a b a b a b a b 10 a b cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 hlat = 001 (binary), tlsz = 01 (binary), lram = 0 (binary), ldev = 0 (binary). note: |(lhi_0[6:0]) and &(lhi_1_l[6:0]) stands for the boolean ?or? and ?and? respectively of the entire lhi bus. note: each bit in lho_0[1:0] and lho_1_l[1:0] is the same logical signal. this timing diagram is for device #0 only, high-z means this device is not driving, but other device in the cascade may be driving the bus. phs_l sadr[ m :0] ssf ssv ale_l m-search1 m-search3 z z z z 0 0 |(lhi_0[6:0]) 0 lho_0[1:0] figure 6-15. timing diagram for 72- bit multisearch device number 0 0 0 z z z z z 0 0 0 0 z z z z z 1 1 1 1 z z z z z 1 1 1 1 z z hit miss hit miss hit miss hit &(lhi_1_l[6:0]) 1 lho_1_l[1:0] 0 1 1 0 0 1 m-search5 cycle 11 cycle 12 0 0 1 1 0 sram interface signals cascade signals in multisearch mode a c e g f dh b i j addr addr z z addr addr z z z addr addr a c e h i j m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 z z z 1 1 1 1 z z [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 69 of 153 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] m-search2 m-search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 hlat = 001 (binary), tlsz = 01 (binary), lram = 0 (binary), ldev = 0 (binary). note: |(lhi_0[6:0]) and &(lhi_1_l[6:0]) stands for the boolean ?or? and ?and? respectively of the entire lhi bus. note: each bit in lho_0[1:0] and lho_1_l[1:0] is the same logical signal. phs_l sadr[ m :0] ssf ssv ale_l 10 10 10 10 m-search1 m-search3 a b a b a b a b addr z z z z z 0 0 |(lhi_0[6:0]) lho_0[1:0] figure 6-16. timing diagram for 72-bit multisearch device number 1 addr z hit - this miss local hit miss hit miss miss z z 0 0 z z z 1 1 z 1 1 z z device is global winner but not global winner &(lhi_1_l[6:0]) lho_1_l[1:0] 1 0 1 0 0 0 1 1 0 1 0 1 z z 10 m-search5 a b 0 1 1 0 0 1 0 sram interface signals cascade signals in multisearch mode a c e g f dh b i j b f m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 miss 1 1 z z z [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 70 of 153 ? when more than one device is cascaded, the last device is always the default driver of the sram interface signals, i.e., when none of the devices is driving, the last device will set the sram interface signals to a known default state. when other device s are driving, the last device will set its i/os on the sram interface to high-z. ? referring to figure 6-17 , the last device drives the sram interface signal s until the end of cycle #5. from cycle #6 onwards, its i/os are three-stated to allow other devi ces to drive the sram interface signals, exce pt when it?s its turn to drive. this goes on until the end of cycle #1 0, and at the beginning of cycle #1 1, it drives the sram interfac e to a known default state again when no other devices are driving. cycle clk2x cmdv cmd[1:0] dq ce_l oe_l miss on cmd[10:2] m-search2 m-search4 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 hlat = 001 (binary), tlsz = 01 (binary), lram = 1 (binary), ldev = 1 (binary). note: |(lhi_0[6:0]) and &(lhi_1_l[6:0]) stands for the boolean ?or? and ?and? respectively of the entire lhi bus. note: each bit in lho_0[1:0] and lho_1_l[1:0] is the same logical signal. phs_l sadr[ m :0] ssf ssv 10 10 10 10 m-search1 m-search3 a b a b a b a b 0 local winner but not global winner |(lhi_0[6:0]) lho_0[1:0] this device 0 z 0 ale_l we_l global winner z figure 6-17. timing diagram for 72-bit multisearch device number 7 (last device) a c e g f dh b addr addr z 0 0 z 0 0 miss on this device local but not global winner global winner &(lhi_1_l[6:0]) lho_1_l[1:0] 10 m-search5 a b i j 0 01 1 z 0 0 0 0 1 0 1 1 1 1 1 0 0 1 1 1 1 z z z 0 z 1 0 z 1 z 0 0 1 z z z z z 0 0 0 ?gray area? = the last device is driving the bus to a known state. sram interface signals cascade signals in multisearch mode d g m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 0 z 1 0 z 1 z [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 71 of 153 the following is the sequence of operation for a si ngle 72-bit multisearch command (also refer to subsection 6.2, ?command bus parameters,? on page 50 ). ? cycle a : ? command bus : the host asic drives cmdv high and applies sear ch command cmd[1:0] = ?10?. the cmd[2] signal must be driven to logic 0. {cmd[10], cmd[5:3]} signals must be driven with the index to the gmr pair for use in this search operation. cmd[7:6] signals must be driven with the same bits that will be driven on sadr[24:23] for cynse10512, sadr[23:22] for cynse10256, sadr[ 22:21] for CYNSE10128 by this device if it has a hit. cmd[8] must be set to logic 1, and cmd[9] must be set to logic 0. ? dq bus : dq[71:0] must be driven with the 72-bit data to be compar ed against the upper half (array 0) of the device entries. ? cycle b : ? command bus : the host asic continues to drive cmdv high and to apply search command cm d[1:0] = ?10?. cmd[5:2] must be driven with the index of the comparand register. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry a nd the hit flag (see page 27 for information on ssr[0:7]). cmd[10:9] are don?t ca res during this cycle. ? dq bus : the dq[71:0] is driven with the data that needs to co mpared with lower half (array 1) of the device entries. the logical 72-bit search operation is shown in figure 6-18 . the upper half of the device cons isting of 72-bit entries is compared to a 72-bit word that is presented on the dq bus in cycles a us ing the gmr and local mask bits. t he gmr used is the 72-bit word specified in the ev en gmr selected by the gmr index in the command?s cycle a. the lower hal f of the device consisting of 72- bit entries is compared to a 72-bit word that is presented on th e dq bus in cycles b using the gmr and local mask bits. the gmr used is the 72-bit word specified in the odd gmr selected by the gmr index in the comm and?s cycle a. the result of the two searches from the two halves are driven as two sram cycles as shown in the timing diagram. a ma tching entry from each array that satisfies the soft priority and mini-key scheme will be the winning entries, and their location addresses la and lb will b e driven as part of the sram addr ess on the sadr[n:0] lines (see section 6.7, ?sram pio access,? on page 121 ), n = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128. the search command is a pipelined operation and executes a s earch at the frequency of clk2x for 72-bit searches in 72- configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 72-bit search co mmand cycle (two clk2x cycles) is shown in ta ble 6-4 . search latency from command to sram access cycle is 5 from a single devi ce upto eight devices in the table with tlsz = 01. in addition, ssv and ssf sh ift further to the right for different values of hlat, as specified in table 6-5 . 71 0 location 0 1 2 3 n/2 - 1 (72-bit configuration) address data from cycle a gmr(even) 71 0 (first matching entry in la figure 6-18. 72 table with in multisearchmode 71 0 location n/2 n/2 + 1 n/2 + 2 n/2 + 3 n-1 address data from cycle b gmr 71 0 (first matching entry in lb the lower half) the upper half) upper half (array 0) lower half (array 1) n = 262144 for cynse10512 131072 for cynse10256 65536 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 72 of 153 6.5.5 144-bit single search for cascade up to 31 devices the hardware diagram of the search s ubsystem of 31 devices is shown in figure 6-19 . each of the four blocks in the diagram represents eight ayama 10000 devices (except the last, which ha s seven devices). the diagram fo r a block of eight devices is very similar to the hardware diagram in figure 6-9 , except that the bhi[2:0] signals are connected to bho of the previous block (rather than being grounded) as shown in figure 6-9 . the following are the parameters programmed into the 31 devices: ? first thirty devices (devices 0?29): tlsz = 10 (binary), hlat = 001 (binary), lram = 0 (binary), and ldev = 0 (binary). ? thirty-first device (device 30): tlsz = 10 (binary), hlat = 001 (binary), lram = 1 (binary), and ldev = 1 (binary). ? for non-enhanced mode, cfg[63:0] = 5555555555555555 (hex) for all devices for cynse10512. cfg[31:0] = 55555555 (hex) for all devices for cynse10256, a nd cfg[15:0] = 5555 (hex) for all devices for CYNSE10128. for enhanced mode, nes in each block for all devices should be set to ?01? to create 144-bit table. ? the device receiving all the lho signals from the other devices is considered the last device. ? all the shared signals showing tri-stated condition (?z?) indica te that, that particular devic e is not driving the shared sign als. the shared signals are not three-stated in a real life because other devices will be driving them. ? comparing the hardware diagrams shown in figure 6-9 and figure 6-14 , enabling multisearch does not mean that a board layout change is required. the lho_1_l and lhi_1_l share the sa me pin with the full in and full out signals, which are not shown in figure 6-9 . cascading multiple devices togethe r still allow the user to configur e the devices through software to perform single-search or multisearch operations without any board change. the timing diagrams referred to in this paragraph reference the hit/miss assumptions defined in table 6-8 . for the purpose of illustrating the timings, it is further a ssumed that there is only one device with a matching entry in each of the blocks. figure 6- 20 shows the timing diagram for a search command in the 144-bit-c onfigured table of 31 devices for each of the eight devices in block number 0. figure 6-21 shows the same for the all the devices in block number 1 (above the winning device in that block). figure 6-22 shows the timing diagram for the globally winning device (defined as the final winner within its own and all blocks) in block number 1. figure 6-23 shows the timing diagram for all the devices below the globally winning device in block number 1. figure 6-24 , figure 6-25 , and figure 6-26 show the timing diagrams of the devices above the globally winning device, the globally winning device, and the devices below the globally winning device, respectively, for block number 2. figure 6-27 , figure 6-28 , figure 6-29 , and figure 6-30 show the timing diagrams of the devices above globally winning device, the globally winning device, and the devices below the globally winning device except the last device (device 30), respectively, for block number 3. the 144-bit search operation is pi pelined and executes as follows: ? four cycles from the search command, each of the devices knows the outcome internal to it fo r that operation. ? on the fifth cycle, the devices arbitrate for a winner within a block (a ?block? is defined as less than or equal to eight dev ices resolving the winner within them using the lh i[6:0] and lho[1:0] signalling mechanism). ? on the sixth cycle after the search comm and, the blocks (of devices) resolve the winning block through the bhi[2:0] and bho[2:0] signalling mechanism. the winning devic e within the winning block is the global winning device for a search operation. table 6-8. hit/miss assumptions search number 1 2 3 4 block 0missmissmissmiss block 1 miss miss hit miss block 2 miss hit hit miss block 3 hit hit miss miss [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 73 of 153 gnd bho[2] block of 8 ayama 10000s block 0 bho[1] bho[0] bhi[2] bhi[1] bhi[0] bhi[2] block of 7 ayama 10000s block 3 bhi[1] bhi[0] gnd bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bhi[2] bhi[1] bhi[0] gnd block of 8 ayama 10000s block 1 block of 8 ayama 10000s block 2 dq[71:0] sram bho[2] bho[2] bho[1] bho[1] bho[0] bho[0] cmd[10:0], cmdv ssf, ssv (devices 8?15) (devices 16?23) (devices 24?30) (devices0?7) figure 6-19. hardware diagram for a table with 31 devices [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 74 of 153 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 hlat = 001 (binary), tlsz = 10 (binary), lram = 0 (binary), ldev = 0 (binary). note: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the bool ean ?or? for the ent ire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[ m :0] ssf ssv ale_l search1 search2 search4 10 10 10 10 search1 search3 a b a b a b a b z z z z z z z lho[1:0] 0 i(bhi[2:0]) 0 (miss on this device) search3 |(lhi[6:0]) 0 bho[2:0] 0 w1 w2 x1 x2 y1 y2 z1 z2 dq d1 d2 d3 d4 (miss on this device) (miss on this device) (miss on this device) figure 6-20. 144-bit search for devices in block #0 and above block #1 winning device m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 75 of 153 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 hlat = 001 (binary), tlsz = 10 (binary), lram = 0 (binary), ldev = 0 (binary). note: |(bhi[2:0]) stands for the bool ean ?or? of the enti re bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[ m :0] ssf ssv ale_l search1 search2 search4 10 10 10 10 search1 search3 a b a b a b a b z z z z z z z lho[1:0] 0 (miss on this device) (miss on this device) i(bhi[2:0]) 0 (miss on this device) (this device global winner) |(lhi[6:0]) 0 bho[2:0] 0 addr w1 w2 x1 x2 y1 y2 z1 z2 dq d1 d2 d3 d4 1z 1 z 1z 0 z 0 z z search3 figure 6-21. 144-bit search timing diagram for block #1 global winning device y m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 76 of 153 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 hlat = 001 (binary), tlsz = 10 (binary), lram = 0 (binary), ldev = 0 (binary). note: |(bhi[2:0] stands for the boolean ?or? of the entire bus bhi[2:0]. note: |(lhi(6:0) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[ m :0] ssf ssv ale_l search1 search2 search4 10 10 10 10 search1 search3 a b a b a b a b z z z z z z z lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] 0 w1 w2 x1 x2 y1 y2 z1 z2 dq d1 d2 d3 d4 (miss on this device) (miss on this device) (miss on this device) (miss on this device) figure 6-22. 144-bit search timing diagra m for devices below block #1 winning device m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 77 of 153 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 hlat = 001 (binary), tlsz = 10 (binary), lram = 0 (binary), ldev = 0 (binary). note: |(bhi[2:0]) stands for the bool ean ?or? of the enti re bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[ m :0] ssf ssv ale_l search1 search2 search4 10 10 10 10 search1 search3 a b a b a b a b z z z z z z z lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] 0 w1 w2 x1 x2 y1 y2 z1 z2 dq d1 d2 d3 d4 (miss on this device) (miss on this device) (miss on this device) (miss on this device) figure 6-23. 144-bit search timing diagra m for devices above block #2 winning device m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 78 of 153 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 hlat = 001 (binary), tlsz = 10 (binary), lram = 0 (binary), ldev = 0 (binary). note: |(bhi[2:0]) stands for the bool ean ?or? of the enti re bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[ m :0] ssf ssv ale_l search1 search2 search4 10 10 10 10 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 (global winner) i(bhi[2:0]) 0 search3 (hit but not winner) |(lhi[6:0]) 0 bho[2:0] 0 addr 0 z 0 1 1 1 z z z z z z w1 w2 x1 x2 y1 y2 z1 z2 dq d1 d2 d3 d4 (miss on this device) (miss on this device) figure 6-24. 144-bit search timing diagram for block #2 global winning device x m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 79 of 153 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 hlat = 001 (binary), tlsz = 10 (binary), lram = 0 (binary), ldev = 0 (binary). note: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boole an ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[ m :0] ssf ssv ale_l search1 search2 search4 10 10 10 10 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] 0 z w1 w2 x1 x2 y1? y2 z1 z2 dq d1 d2 d3 d4 (miss on this device) (miss on this device) (miss on this device) (miss on this device) figure 6-25. 144-bit search timing diagram for devices below block #2 winning device m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 80 of 153 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 hlat = 001 (binary), tlsz = 10 (binary), lram = 0 (binary), ldev = 0 (binary). note: |(bhi[2:0]) stands for the bool ean ?or? of the enti re bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[ m :0] ssf ssv ale_l search1 search2 search4 10 10 10 10 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] 0 z w1 w2 x1 x2 y1 y2 z1 z2 dq d1 d2 d3 d4 (miss on this device) (miss on this device) (miss on this device) (miss on this device) figure 6-26. 144-bit search timing diagra m for devices above block #3 winning device m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 81 of 153 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 hlat = 001 (binary), tlsz = 10 (binary), lram = 0 (binary), ldev = 0 (binary). note: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boole an ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[ m :0] ssf ssv ale_l search1 search2 search4 10 10 10 10 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 (hit but not global winner) (miss on this device) i(bhi[2:0]) 0 (global winner) search3 (miss on this device) |(lhi[6:0]) 0 bho[2:0] 0 addr 0 z 0 1 1 1 z z z z z z w1 w2 x1 x2 y1 y2 z1 z2 dq d1 d2 d3 d4 figure 6-27. 144-bit search timing diagram for block #3 global winning device w m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 82 of 153 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 hlat = 001 (binary), tlsz = 10 (binary), lram = 0 (binary), ldev = 0 (binary). note: |(bhi[2:0]) stands for the bool ean ?or? of the enti re bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[ m :0] ssf ssv ale_l search1 search2 search4 10 10 10 10 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] 0 z w1 w2 x1 x2 y1 y2 z1 z2 dq d1 d2 d3 d4 (miss on this device) (miss on this device) (miss on this device) (miss on this device) figure 6-28. 144-bit search diagram below bl ock #3 winning device except the last device m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 83 of 153 the following is the sequence of operation for a single 144-bit search command (also refer to subsection 6.2, ?command bus parameters,? on page 50 ). ? cycle a : ? command bus : the host asic drives cmdv high and applies search command cmd[1:0] = ?10? (binary). cmd[2] must be driven to logic low. {cmd[10],cmd[5:3]} signals must be driv en with the index to the gmr pair for use in this search operation. cmd[8:6] signals must be driven with the same bits that will be driven on sadr[25:23] for cynse10512, sadr[24:22] for cynse10256, sadr[2 3:21] for CYNSE10128 by this dev ice if it has a hit. cmd[9] must be driven to logic high to indicate a 144-bit search. ? dq bus : dq[71:0] must be dr iven with the 72-bit data to be compared. ? cycle b : ? command bus : the host asic continues to drive cmdv high and applies search command cmd[1:0] = ?10? (binary). cmd[5:2] must be driven by the index of the comparand register pair for storing the 144-bit word presented on the dq bus cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 hlat = 001 (binary), tlsz = 10 (binary), lram = 1 (binary), ldev = 1 (binary). note: |(bhi[2:0)] stands for the bool ean ?or? of the enti re bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[ m :0] ssf ssv ale_l search1 search2 search4 10 10 10 10 search1 search3 a b a b a b a b z 0 0 lho[1:0] 0 (global miss; this device is default driver) i(bhi[2:0]) 0 search3 (hit on some device above) |(lhi[6:0]) 0 bho[2:0] 0 z 0 0 0 z 1 z 1 0 0 z z 0 1 w1 w2 x1 x2 y1 y2 z1 z2 dq d1 d2 d3 d4 (hit on some device above) (hit on some device above) figure 6-29. 144-bit search timing diagram for device number 6 in block #3 m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 84 of 153 during cycles a and b. cmd[ 8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and the hi t flag (see page 27 for the descrip tion of ssr[0:7]). cmd[10:9] are don?t cares in this cycle. ? dq bus : the dq[71:0] continues to carry the 72-bit data to be compared. the logical 144-bit search operation is shown in figure 6-30 . the entire table of 31 devices (consisting of 72-bit entries) is compared to a 144-bit word k presented on the dq bus in bo th cycles a and b of the command using the gmr and local mask bits. the gmr is the 144- bit word specified by t he even and odd gmr pairs selected by the gmr index in the command?s cycle a. the 144-bit word k (presented on the dq bus in both cycles a and b of the command) is also stored in both even and odd comparand register pairs selected by the comparand regist er index in command cycl e b. in the 144 config uration, the even and odd comparand register can be subsequently used by the learn command only in the first non-full device. note . the learn command is supported for only one of the blocks consisting of up to eight devices in a depth-cascaded table of more than one block. the word k (presented on the dq bus in both cycles a and b of th e command) is compared with eac h entry in the table, starting at location 0 (decimal). a matching entry that satisfies the so ft priority and mini-key scheme (for enhanced mode) will be the winning entry, and its location address l will be driven as part of the sram addre ss on the sadr[n:0] lines (see ?sram pio access? on page 121 ), n = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128. the global winning device will drive the bus in a specific cycle. on global miss cycles, the device with lram = 1 (binary) and ldev = 1 (binary) will be the default driver for such missed cycles. note . during 144-bit searches of 144-bi t-configured tables, the search hi t will always be at an even address. the search command is a pipelined operation and executes a search at half the rate of the frequency of clk2x for 144-bit searches in 144-configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 144-bit search command cycle (two clk2x cycles) is shown in table 6-4 . for up to 31 devices in the table (tlsz = 10 (binary)), search latency is 6 from command to sram access cycle. in addition, ssv and ssf shift further to t he right for different values of hlat, as specified in table 6-5 . 143 0 location 0 2 4 6 n (144-bit configuration) address k gmr comparand register (odd) comparand register (even) a b 143 0 71 0 (first matching entry) l a b even odd will be same in each of the 31 devices must be same in each of the 31 devices figure 6-30. 144 table with 31 devices n = 4063231 for cynse10512 2031615 for cynse10256 1015807 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 85 of 153 6.5.6 576-bit single search for one de vice or cascade up to eight devices the hardware diagram of the search subsystem of up to eight devices is shown in figure 6-9 . the multisearch enable (mse) bit in the command register must be set low to perform single-s earch. the following are the rest of the parameters programmed into the eight devices. ? first seven devices (devices 0?6): tl sz = 01 (binary), hlat = 000 (binary), lram = 0 (binary), and ldev = 0 (binary). ? eighth device (device 7): tlsz = 01 (binary), hlat = 000 (binary), lram = 1 (binary), and ldev = 1 (binary). ? 576-bit search is only available in the enhanced mode, not in the non-enhanced mode. nes should be set to ?11? (binary) in all blocks of all devices to create a 576-bit table. for a single-device configuration, all para meters will be the same as device 7. bhi[2: 0] and lhi[6:0] should be tied to ground. notes : ? all eight devices must be programmed with the same values fo r tlsz and hlat. only the last device in the table (device number 7 in this case) must be programmed with lram = 1 (binary) and ldev = 1 (binary). all other upstream devices (devices 0 through 6 in this case) must be programm ed with lram = 0 (binary) and ldev = 0 (binary). ? the device receiving all the lho signals from the other devices is considered the last device. ? all the shared signals in the following timing diagrams showing tri-stated condition (?z?) indica te that, that particular devi ce is not driving the shared signals. the shared si gnals are not three-stated in a real lif e because other devices will be driving th em. ? comparing the hardware diagrams shown in figure 6-9 and figure 6-14 , enabling multisearch does not mean that a board layout change is required. the lho_1_l and lhi_1_l share the sa me pin with the full in and full out signals, which are not shown in figure 6-9 . cascading multiple devices togethe r still allow the user to configur e the devices through software to perform single-search or multisearch operations without any board change. the following three figures show the response of three of the ei ght devices having a hit at different time according to a hit/m iss assumption shown below in table 6-9 . for these timing diagrams, three 576-bit searches are performed sequentially. figure 6- 31 shows the timing diagram for a search command in the 576- bit-configured table of eight devices for device number 0. figure 6- 32 and figure 6-33 shows the same for device number 1 and number 7 (the last device in this specific table) respectively. table 6-9. hit/miss assumptions search number 1 2 3 device 0 hit miss miss device 1 miss hit miss devices 2?6 miss miss miss device 7 miss miss miss [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 86 of 153 b search2 10 10 10 a b a b a a b cycle clk2x cmdv cmd[1:0] dq ce_l oe_l (this cmd[10:3] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 hlat = 000 (binary), tlsz = 01 (binary), lram = 0 (binary), ldev = 0 (binary). note: |(lhi[6:0]) stands for the bool ean ?or? of the entire bus lhi[6:0]. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[ m :0] ssf ssv ale_l search1 search3 search1 search3 addr z z z z z z z 0 0 0 1 1 1 device is the global winner) |(lhi[6:0]) 0 this device) (miss on this device) lho[1:0] search2 (miss on figure 6-31. timing diag ram for 576-bit single search device number 0 cycle 11 cycle 12 cycle 13 cycle 14 cycle 15 cycle 16 a b a b a b a b a b a b a b a b a6 a1 a2 a3 a4 a5 a7 a8 b1 b2 b3 b4 b5 b6 b7 b8 c1 c2 c3 c4 c5 c6 c7 c8 0 z z z z z z 1 cmd[2] the 4th a-cycle cmpr[2] on b-cycles logic 1 for 3 a-cycles logic 0 on a m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 87 of 153 b search2 10 10 10 a b a b a a b cycle clk2x cmdv cmd[1:0] dq ce_l oe_l (miss on cmd[10:3] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 hlat = 000 (binary), tlsz = 01 (binary), lram = 0 (binary), ldev = 0 (binary). note: |(lhi[6:0]) stands for the bool ean ?or? of the entire bus lhi[6:0]. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[ m :0] ssf ssv ale_l search1 search3 search1 search3 addr z z z z z z z 0 0 0 1 1 1 this device) |(lhi[6:0]) is the global (miss on this device) lho[1:0] search2 (this device figure 6-32. timing diagram for 576- bit single search device number 1 cycle 11 cycle 12 cycle 13 cycle 14 cycle 15 cycle 16 a b a b a b a b a b a b a b a b a6 a1 a2 a3 a4 a5 a7 a8 b1 b2 b3 b4 b5 b6 b7 b8 c1 c2 c3 c4 c5 c6 c7 c8 0 z z z z z z 0 0 winner) 1 1 cmd[2] the 4th a-cycle cmpr[2] on b-cycles logic 1 for 3 a-cycles logic 0 on b m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 88 of 153 the following is the sequence of operation for a single 576-bit search command (also refer to subsection 6.2, ?command bus parameters,? on page 50 ). ? cycle a : ? command bus : the host asic drives cmdv high and applies search command cmd[1:0] = ?10? (binary). cmd[2] must be driven to logic 1 for the first three a-cycles and then driven to logic 0 for the final a-cycle for 576-bit search. b search2 10 10 10 a b a b a a b cycle clk2x cmdv cmd[1:0] dq ce_l oe_l (miss on cmd[10:3] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 hlat = 000 (binary), tlsz = 01 (binary), lram = 1 (binary), ldev = 1 (binary). note: |(lhi[6:0]) stands for the bool ean ?or? of the entire bus lhi[6:0]. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[ m :0] ssf ssv ale_l search1 search3 search1 search3 z z 0 0 0 this device) |(lhi[6:0]) (miss on this device) lho[1:0] search2 figure 6-33. timing diagram for 576-bit si ngle search device number 7 (last device) cycle 11 cycle 12 cycle 13 cycle 14 cycle 15 cycle 16 a b a b a b a b a b a b a b a b cmd[2] a6 a1 a2 a3 a4 a5 a7 a8 b1 b2 b3 b4 b5 b6 b7 b8 c1 c2 c3 c4 c5 c6 c7 c8 0 z z 0 0 1 1 0 z 0 z 0 z 1 z 1 0 z 0 z 0 (miss on this device) logic 1 for 3 a-cycles logic 0 on the 4th a-cycle cmpr[2] on b-cycles m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 1 z z 0 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 89 of 153 {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair for use in this search operation. each of the four a-cycles provide a gmr index to mask 144 bits of the data to be compared (each a-cycle provide a pair of gmr, which is 144 bits, for a-cycles will result in a total of 576 bits of gmr). cmd[8:6] signals must be driven with the same bits that will be driven on sadr[25:23] for cyn se10512, sadr[24:22] for cynse10256, sadr[23:21] for CYNSE10128 by this device if it has a hit. cmd[9] is don?t care for this cycle. ? dq bus : at the same time in cycle a, dq[71:0] must be driv en with 72-bit data (which is pa rt of the 576-bit data) to be compared. ? cycle b : ? command bus : the host asic continues to drive cmdv high and to apply search command cmd[1:0] = ?10? (binary). cmd[5:2] must now be driven by the index of the comparand r egister pair for storing the tw o 72-bit word presented on the dq bus during cycles a and b. each of the four b-cycles provid e an index for a pair of comparand register. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and hit flag (see page 27 for a description of ssr[0:7]). cmd[10:9] ar e don?t cares for this cycle. ? dq bus : the dq[71:0] continues to carry the 72-bit data (which is part of the 576-bit data) to be compared. note . for 576-bit searches, the host asic must supply individual 72-bit data on dq[71:0] during cycles a and b. also, four individual pairs of gmr and cmpr registers may be involved in the comparison. the logical 576-bit search operation is shown in figure 6-34 . the entire table of 576-bit entries (eight devices) is compared to a 576-bit word k that is present ed on the dq bus in eight cycles using the gmr and local mask bits . the gmr is the 576-bit word specified by four pairs of gmrs selected by gmr indices in each of the eigh t devices. the 576-bit word k (presented on the dq bus in all eight cycles of the command) is also stored in both even and odd comparand register pairs (selected by the comparand register index in command cycle b) in each of the eight devices. the word k is compar ed with each entry in the table, starting at location 0 (decimal). a matching entry that satisfies the soft priority and mini-key scheme will be the winning entry, and its location address l will be driven as part of the sr am address on the sadr[n:0] lines (see section 6.7, ?sram pio access,? on page 121 ), n = 25 for cynse10512, 24 for cynse10256, 23 for cy nse10128. the global winning device will drive the bus in a specific cycle. on a global miss cycle, th e device with lram = 1 (bin ary) (default driving device for the sram bus) and ldev = 1 (binary) (default driving device fo r ssf and ssv signals) will be the de fault driver for such missed cycles. the search command is a pipelined operation a nd executes a search at one-eighth the ra te of the frequency of clk2x for 576-bit searches in 576-configured tabl es. the latency of the search from command to sram access cycle is 5 for up to eight devices in the table (tlsz = ?01? (binary)). ssv and ssf also shift furt her to the right for different va lues of hlat, as specified in table 6-5 . 6.5.7 576-bit multisearch for one device or cascade up to eight devices the multisearch operates the sear ch commands in parallel on the upper and lower half (array 0 and 1) of the device. the results from the two parallel searches are then driven on the sr am bus at twice that rate relative to a single-search. notes : ? for x72 multi searches, two individual 72-bit search keys can be searched in array 0 and array 1 simultaneously. for x144, x288 and x576 multi searches, both arrays will be searched with the same 144-bit, 288- bit or 576-bit search keys respectively. 576 0 location 0 1 2 3 n (576-bit configuration) address k gmr comparand register (odd) comparand register (even) k k 576 0 71 0 (first matching l must be same in each of the eight devices will be same in each of the eight devices figure 6-34. 576 table with eight devices entry) n = 262143 for cynse10512 131071 for cynse10256 65535 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 90 of 153 ? in multisearch mode, there is a separate set of the lho a nd lhi signals corresponding to memory array 0 and array 1. lho_0[1:0] and lhi_0[ 6:0] corresponds to array 0 whereas lho_1_l[1:0] and lhi_1_l[6:0] corre sponds to array 1. the latter share the same pins as fulo[1:0] and fuli[6:0] respectively. ? both lho_0[1] and lho_0[ 0] are exact same signals so that the loads can be shared by two outputs. the same is true for lho_1_l[1] and lho_1_l[0]. ? unused lhi_0 signals should be tied to ground whereas unused lhi_1_l signals should be tied to v ddq_asic , which is either 1.8v or 2.5v only. ? lhi_1_l signals are active low while lhi_0 are active high. the hardware diagram of the multisearch subsystem of up to eight devices is shown in figure 6-14 . the multisearch enable (mse) bit in the command register must be set high to perf orm multi search. the same wi th enhanced mode (emode) bit. the following are the rest of the parame ters programmed into the eight devices. ? first seven devices (devices 0?6): tl sz = 01 (binary), hlat = 000 (binary), lram = 0 (binary), and ldev = 0 (binary). ? eighth device (device 7): tlsz = 01 (binary), hlat = 000 (binary), lram = 1 (binary), and ldev = 1 (binary). ? nes (in the block mini-key register) field in each block of all devices must be set to ?11? (binary) to make a 576-bit table. for a single-device configuration, all para meters will be the same as device 7. bhi[2: 0] and all lhi should be tied to ground. notes : ? the device receiving all the lho signals from the other devices is considered the last device. ? all the shared signals in the following timing diagrams showing tri-stated condition (?z?) indica te that, that particular devi ce is not driving the shared signals. the shared si gnals are not three-stated in a real lif e because other devices will be driving th em. ? comparing the hardware diagrams shown in figure 6-9 and figure 6-14 , enabling multisearch does not mean that a board layout change is required. the lho_1_l and lhi_1_l share the sa me pin with the full in and full out signals, which are not shown in figure 6-9 . cascading multiple devices together still allows the us er to configure the devices through software to perform single-search or multisearch operations without any board change. the following three figures show the response of three of the ei ght devices having a hit at different time according to a hit/m iss assumption shown below in ta ble 6-1 0 . for these timing diagrams, three 576-bit searches are performed sequentially. figure 6- 35 shows the timing diagra m for a multisearch command in the 576-bit-config ured table of eight devices for device number 0. figure 6-36 and figure 6-37 shows the same for device number 1 and number 7 (the last device in this specific table) respectively. table 6-10. hit/mi ss assumptions for 576-bit multi search search number 1 2 3 device 0 hit hit miss miss miss miss device 1 miss miss hit miss miss miss devices 2?6 miss miss miss miss miss miss device 7 miss miss miss hit miss miss [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 91 of 153 b multi search2 10 10 10 a b a b a a b cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:3] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 hlat = 000 (binary), tlsz = 01 (binary), lram = 0 (binary), ldev = 0 (binary). note: |(lhi_0[6:0]) and &(lhi_1_l[6:0]) stands for the boolean ?or? and ?and? of the entire lhi bus. note: each bit in lho_0[1:0] and lho_1_l[1:0] is the same logical signal. phs_l sadr[ m :0] ssf ssv ale_l multi search1 multi search3 z z z z z z z 0 0 0 1 1 1 ( lhi_0[6:0]) 0 lho_0[1:0] cycle 11 cycle 12 cycle 13 cycle 14 cycle 15 cycle 16 a b a b a b a b a b a b a b a b a6 a1 a2 a3 a4 a5 a7 a8 b1 b2 b3 b4 b5 b6 b7 b8 c1 c2 c3 c4 c5 c6 c7 c8 0 z z z z z z 1 cmd[2] the 4th a-cycle cmpr[2] on b-cycles logic 1 for 3 a-cycles logic 0 on multi-search1 multi-search2 (miss on this device) multi-search3 (miss on this device) &(lhi_1_l[6:0]) 1 l ho_1_l[1:0] 1 0 1 (hit in both arrays) figure 6-35. timing diagram for 576-bit multisearch device number 0 addr a addr a m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 92 of 153 hlat = 000 (binary), tlsz = 01 (binary), lram = 0 (binary), ldev = 0 (binary). note: |(lhi_0[6:0]) and &(lhi_1_l[6:0]) stands for the boolean ?or? and ?and? of the entire lhi bus. note: each bit in lho_0[1:0] and lho _1_l[1:0] is the same logical signal. b multi-search2 10 10 10 a b a b a a b cycle clk2x cmdv cmd[1:0] dq ce_l oe_l (miss on cmd[10:3] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[ m :0] ssf ssv ale_l multi-search1 multi-search3 multi-search1 multi-search3 z 0 this device) (miss on this device) multi-search2 (hit on array 0, figure 6-36. timing diagram for 576-bit multisearch device number 1 cycle 11 cycle 12 cycle 13 cycle 14 cycle 15 cycle 16 a b a b a b a b a b a b a b a b a6 a1 a2 a3 a4 a5 a7 a8 b1 b2 b3 b4 b5 b6 b7 b8 c1 c2 c3 c4 c5 c6 c7 c8 0 0 0 1 1 cmd[2] the 4th a-cycle cmpr[2] on b-cycles logic 1 for 3 a-cycles logic 0 on 1 1 0 | (lhi_0[6:0]) lho_0[1:0] &(lhi_1_l[6:0]) lho_1_l[1:0] 0 addr z z z 0 z z 0 z z 1 z z z z z 1 1 miss on array 1 for this device) b m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 93 of 153 hlat = 000 (binary), tlsz = 01 (binary), lram = 0 (binary), ldev = 0 (binary). note: |(lhi_0[6:0]) and &(lhi_1_l[6:0]) stands for the boolean ?or? and ?and? of the entire lhi bus. note: each bit in lho_0[1:0] and lho_1_l[1:0] is the same logical signal. b multi-search2 10 10 10 a b a b a a b cycle clk2x cmdv cmd[1:0] dq ce_l oe_l (miss on this device cmd[10:3] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[ m :0] ssf ssv ale_l multi-search1 multi-search3 multi-search1 multi-search3 z z 0 0 0 0 on both arrays) (miss on this device) multi-search2 figure 6-37. timing diagram for 576-bit multisearch device number 7 (last device) cycle 11 cycle 12 cycle 13 cycle 14 cycle 15 cycle 16 a b a b a b a b a b a b a b a b cmd[2] a6 a1 a2 a3 a4 a5 a7 a8 b1 b2 b3 b4 b5 b6 b7 b8 c1 c2 c3 c4 c5 c6 c7 c8 0 z z 0 0 0 1 1 0 z 0 0 z 1 1 z 0 0 0 0 (miss in array 1 hit on array 2 logic 1 for 3 a-cycles logic 0 on the 4th a-cycle cmpr[2] on b-cycles (lhi_0[6:0]) lho_0[1:0] &(lhi_1_l[6:0]) lho_1_l[1:0] 0 1 1 addr for this device) z z z 1 z z 1 b m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 1 1 0 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 94 of 153 the following is the sequence of operation for a single 576-bit search command (also refer to subsection 6.2, ?command bus parameters,? on page 50 ). ? cycle a : ? command bus : the host asic drives cmdv high and applies search command cmd[1:0] = ?10? (binary). cmd[2] must be driven to logic 1 for the first three a-cycles and then driven to logic 0 for the final a-cycle for 576-bit search. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair for use in this search operation. each of the four a-cycles provide a gmr index to mask 144 bits of the data to be compared. cmd[7:6] signals must be driven with the same bits that will be driven on sadr[24:23] for cy nse10512, sadr[23:22] for cy nse10256, sadr[22:21] for CYNSE10128 by this device if it has a hit. cmd[8] must be driven high for every a-cycl e. cmd[9] is don?t care for this cycle. ? dq bus : at the same time in cycle a, dq[71:0] must be driv en with 72-bit data (which is pa rt of the 576-bit data) to be compared. ? cycle b : ? command bus : the host asic continues to drive cmdv high and to apply search command cmd[1:0] = ?10? (binary). cmd[5:2] must now be driven by the index of the comparand r egister pair for storing the tw o 72-bit word presented on the dq bus during cycles a and b. each of the four b-cycles provid e an index for a pair of comparand register. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and hit flag (see page 27 for a description of ssr[0:7]). cmd[10:9] ar e don?t cares for this cycle. ? dq bus : the dq[71:0] continues to carry the 72-bit data (which is part of the 576-bit data) to be compared. note . for 576-bit searches, the host asic must supply individual 72-bit data on dq[71:0] during cycles a and b. also, four individual pairs of gmr and cmpr registers may be involved in the comparison. the logical 576-bit search operation is shown in figure 6-38 . the upper half of the device consisting of 576-bit entries is compared to a 576-bit search key, k t hat is presented on the dq bus in eight clk2x cycles using the gmr and local mask bits. the same also happens in the lower half of the devic e. the gmr is the 576-bit word specified by four pairs of gmrs selected by gmr indices in each of the eight de vices. the 576-bit word k (pres ented on the dq bus in all eight cycles of the command) is also stored in both even and odd comparand regi ster pairs (selected by the comparand re gister index in command cycle b) in each of the eight devices. the word k is compared with each entry in the table in both arrays. the winning addresses from both array s will be determined based on the soft priority and mini-key scheme, and the result of the two sear ches from the two halves are driven as part of the sram address on the sadr[n:0] lines (n = 25 for cynse10 512, 24 for cynse10256, 23 for CYNSE10128) with two sram cycles as show n in the timing diagram (see section 6.7, ?sram pio access,? on page 121 ). on a global miss cycle, the device with lram = 1 (binary) ( default driving device for the sram bus) an d ldev = 1 (binary) (default driving device for ssf and ssv signals) will be the default driver for such missed cycles. the search command is a pipelined operation a nd executes a search at one-eighth the ra te of the frequency of clk2x for 576-bit searches in 576-configured tabl es. the latency of the search from command to sram access cycle is 5 for up to eight devices in the table (tlsz = 01 (binary)). ssv and ssf also shift further to the right for different values of hlat, as specified in table 6-5 . 576 0 location 0 1 2 3 n/2 - 1 (576-bit configuration) address k gmr 576 0 (first matching la figure 6-38. 576 tabl e with eight devices entry in the upper 576 0 location n/2 n/2 + 1 n/2 + 2 n/2 + 3 n - 1 address k gmr 576 0 (first matching lb entry in the lowe half) half) upper half (array 0) lower half (array 1) n = 262144 for cynse10512 131072 for cynse10256 65536 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 95 of 153 6.5.8 mixed-size single searches with 31 devi ces on tables configured with different widths this subsection will cover mixed searches (72, 144, and 288) with tables of different widths (72, 144, 288). note : non- enhanced mode does not support 576-bit tables. the sample operat ion shown is for 31 devices, with devices 0 to 7 containing x72 tables (cfg field in command register all zeroes for non- enhanced mode, nes = ?00? (binary) for all blocks for enhanced mode), devices 8 to 15 containing x144 tables (cfg[63:0] field in command register for cynse10512 = 5555555555555555 (hex), cfg[31:0] = 55555555 (hex) for cy nse10256, cfg[15:0] = 5555 (hex) for CYNSE10128 for non-enhanced mode, nes = ?01? (binary) in all blocks for enhanced mode), and the rest of the devices containi ng x288 tables (cfg[63:0] = aaaaaaaaaaaaaaaa (hex) for cynse10512, cfg[31:0] = aaaaaaaa (h ex) for cynse10256, cfg[15:0] = aaaa (hex) for CYNSE10128 for non-enhanced mode, nes = ?1 0? (binary) in all blocks for enhanced mode). the following figures show three sequential searches: first, a 72-bit search on a 72-configured table; a 144-bit search on a 144-configured table; and a 288-bi t search on a 288-configured table that each results in a hit. the 31 cascaded devices can be viewed as three blocks of 8 devices and a fourth block of 7 devices, as shown in figure 6-19 . each individual block of 8 or 7 devices is connected very similarly to the connection shown in figure 6-9 , except that the bhi[2:0] signals are connected to bho of the pr evious block rather than being grounded. figure 6-39 shows a graphical example of the tables using cynse10512s. notes: ? the ?block? in the figure above refers to a block of 8 devices, not a block within a single device. ? all 31 devices must be programmed with the same values for tlz (?10? (binary)) and hlat (?000? (binary) in this example). only the last device in the table must be programmed with lram = 1 (binary) and ldev = 1 (binary) (device 30 in this case). all other upstream devices must be programmed with lram = 0 (b inary) and ldev = 0 (binary) (devices 0 through 29 in this case). ? the device receiving all the lho signals from the other devices is considered the last device. ? all the shared signals in the following timing diagrams showing tri-stated condition (?z?) indica te that, that particular devi ce is not driving the shared signals. the shared si gnals are not three-stated in a real lif e because other devices will be driving th em. ? one way to create many tables of different widths in a bank of nses is by having table designation bits. it is assumed that bits [71:70] for each entry will be assigned such table designation bits. dq[71:70] will be 00 in each of the two a and b cycles of the 72-bit search (search1). dq[71:70] is 01 in each of the a and b cycles of the 144-bi t search (search2). dq[71:70] is 10 in each of the a, b, c, and d cycles of the 288-bit search (search3). the timing diagrams below corresponds to the hit/miss assumptions defined in table 6-11 . for the purpose of illustrating the timings, it is further assumed that there is only one device with a ma tching entry in eac h of the blocks. table 6-11. hit/miss assumptions search number #1 (x72) #2 (x144) #3 (x288) block 0 hit miss miss block 1 miss hit miss block 2 miss miss hit block 3 miss miss miss blocks 2 and 3, devices 16 to 30, 1 mil lion entries block 0, devices 0 to 7, 2 million entries 72 block 1, devices 8 to 15, 1 million entries 144 288 cfg = 0000000000000000 (hex) figure 6-39. multiwidth configurations example with cynse10512s cfg = 5555555555555555 (hex) cfg = aaaaaaaaaaaaaaaa (hex) [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 96 of 153 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 for non-enhanced mode, cfg = all zeroes nes = 00 (binary) in all blo cks for enhanced mode, x72 search hlat = 000 (binary), tlsz = 10 (binary), lram = 0 (binary), ldev = 0 (binary). phs_l sadr[ m :0] ssf ssv ale_l search1 search2 10 10 search1 search3 a b a b a b a b a b1 b2 c1 c2 c3 c4 dq d1 d3 search2 10 d2 miss miss search3 miss figure 6-40. timing diagram for mixed search for devices above block 0 winning device cmd[2] the last a-cycle cmpr[2] on b-cycles logic 0 for a-cycles for x72 and x144 logic 0 on 1st x288 a-cycle logic 1 on the |(lhi[6:0]) 0 0 lho[1:0] |(bhi[2:0]) 0 z z z z z z z m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 97 of 153 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[m:0] ssf ssv ale_l search1 search2 10 10 search1 search3 a b a b a b a b a b1 b2 c1 c2 c3 c4 dq d1 d3 search2 10 d2 hit miss search3 miss figure 6-41. timing diag ram for mixed search for block 0 winning device cmd[2] the last a-cycle cmpr[2] on b-cycles logic 0 for a-cycles for x72 and x144 logic 0 on 1st x288 a-cycle logic 1 on the |(lhi[6:0]) 0 0 lho[1:0] |(bhi[2:0]) 0 0 bho[2:0] z z z z z z z 1 1 0 0 addr z z 0 z 0 z 1 z 1 z 1 from the last device in the block a cfg = all zeroes for non-enhanced mode nes = 00 (binary) in all blo cks for enhanced mode, x72 search hlat = 000 (binary), tlsz = 10 (binary), lram = 0 (binary), ldev = 0 (binary). m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 98 of 153 cfg = all zeroes for non-enhanced mode nes = 00 (binary) in all blocks for enhanced mode, x72 search hlat = 000 (binary), tlsz = 10 (binary), lram = 0, ldev = 0 (binary). cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[n:0] ssf ssv ale_l search1 search2 10 10 search1 search3 a b a b a b a b a b1 b2 c1 c2 c3 c4 dq d1 d3 search2 10 d2 miss on miss on search3 miss on this device figure 6-42. timing diagram for mixed search for devi ces below block 0 winning device cmd[2] the last a-cycle cmpr[2] on b-cycles logic 0 for a-cycles for x72 and x144 logic 0 on 1st x288 a-cycle logic 1 on the |(lhi[6:0]) 0 0 lho[1:0] |(bhi[2:0]) 0 0 bho[2:0] z z z z z z z 1 1 0 0 this device this device from the last device in the block n = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 99 of 153 for non-enhanced mode: cynse10512: cfg[63:0] = 5555555555555555h; cynse10256: cfg[31:0] = 55555555h; CYNSE10128: cfg[15:0] = 5555h. nes = 01 (binary) in all blo cks for enhanced mode, x144 search hlat = 000 (binary), tlsz = 10 (binary), lram = 0 (binary), ldev = 0 (binary). cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[m:0] ssf ssv ale_l search1 search2 10 10 search1 search3 a b a b a b a b a b1 b2 c1 c2 c3 c4 dq d1 d3 search2 10 d2 miss on miss on search3 miss on this device figure 6-43. timing diagram for mixed search above block 1 winning device cmd[2] the last a-cycle cmpr[2] on b-cycles logic 0 for a-cycles for x72 and x144 logic 0 on 1st x288 a-cycle logic 1 on the |(lhi[6:0]) 0 0 lho[1:0] |(bhi[2:0]) 0 z z z z z z z 1 0 this device this device m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 100 of 153 for non-enhanced mode: cynse10512: cfg[63:0] = 5555555555555555h; cynse10256: cfg[31:0] = 55555555h; CYNSE10128, cfg[15:0] = 5555h. nes = 01 (binary) in all blo cks for enhanced mode, x144 search hlat = 000 (binary), tlsz = 10 (binary), lram = 0 (binary), ldev = 0 (binary). cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[m:0] ssf ssv ale_l search1 search2 10 10 search1 search3 a b a b a b a b a b1 b2 c1 c2 c3 c4 dq d1 d3 search2 10 d2 miss on hit on search3 miss on this device figure 6-44. timing diagram for mixed search for block 1 winning device cmd[2] the last a-cycle cmpr[2] on b-cycles logic 0 for a-cycles for x72 and x144 logic 0 on 1st x288 a-cycle logic 1 on the |(lhi[6:0]) 0 0 lho[1:0] |(bhi[2:0]) 0 1 0 this device this device 1 0 bho[2:0] 0 1 0 z z z z z z z addr z z 0 z 0 z 1 z 1 z 1 f rom the last device in the block b m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 101 of 153 for non-enhanced mode: cynse10512: cfg[63:0] = 5555555555555555h; cynse10256: cfg[31:0] = 55555555h; CYNSE10128, cfg[15:0] = 5555h. nes = 01 (binary) in all blo cks for enhanced mode, x144 search hlat = 000 (binary), tlsz = 10 (binary), lram = 0 (binary), ldev = 0 (binary). cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[m:0] ssf ssv ale_l search1 search2 10 10 search1 search3 a b a b a b a b a b1 b2 c1 c2 c3 c4 dq d1 d3 search2 10 d2 miss on miss on search3 miss on this device figure 6-45. timing diag ram for mixed search below block 1 winning device cmd[2] the last a-cycle cmpr[2] on b-cycles logic 0 for a-cycles for x72 and x144 logic 0 on 1st x288 a-cycle logic 1 on the |(lhi[6:0]) 0 0 lho[1:0] |(bhi[2:0]) 0 z z z z z z z 1 0 this device this device 1 0 bho[2:0] 0 1 0 from the last device in the block m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 102 of 153 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[m:0] ssf ssv ale_l search1 search2 10 10 search1 search3 a b a b a b a b a b1 b2 c1 c2 c3 c4 dq d1 d3 search2 10 d2 miss on miss on search3 miss on this device figure 6-46. timing diagram for mixed search above block 2 winning device cmd[2] the last a-cycle cmpr[2] on b-cycles logic 0 for a-cycles for x72 and x144 logic 0 on 1st x288 a-cycle logic 1 on the |(lhi[6:0]) 0 0 lho[1:0] |(bhi[2:0]) 0 z z z z z z z 1 0 this device this device for non-enhanced mode: cynse10512: cfg[63:0] = aaaaaaaaaaaaaaaah; cynse10256: cfg[31:0] = aaaaaaaah; CYNSE10128, cfg[15:0] = aaaah. nes = 10 (binary) in all blo cks for enhanced mode, x288 search hlat = 000 (binary), tlsz = 10 (binary), lram = 0 (binary), ldev = 0 (binary). m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 103 of 153 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[m:0] ssf ssv ale_l search1 search2 10 10 search1 search3 a b a b a b a b a b1 b2 c1 c2 c3 c4 dq d1 d3 search2 10 d2 miss on miss on search3 hit on this device figure 6-47. timing diagram for mixed search for block 2 winning device cmd[2] the last a-cycle cmpr[2] on b-cycles logic 0 for a-cycles for x72 and x144 logic 0 on 1st x288 a-cycle logic 1 on the |(lhi[6:0]) 0 0 lho[1:0] |(bhi[2:0]) 0 1 0 this device this device 1 0 bho[2:0] 0 1 0 z z z z z z z addr z z 0 z 0 z 1 z 1 z 1 f rom the last device in the block c for non-enhanced mode: cynse10512: cfg[63:0] = aaaaaaaaaaaaaaaah; cynse10256: cfg[31:0] = aaaaaaaah; CYNSE10128, cfg[15:0] = aaaah. nes = 10 (binary) in all blo cks for enhanced mode, x288 search hlat = 000 (binary), tlsz = 10 (binary), lram = 0 (binary), ldev = 0 (binary). m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 104 of 153 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[m:0] ssf ssv ale_l search1 search2 10 10 search1 search3 a b a b a b a b a b1 b2 c1 c2 c3 c4 dq d1 d3 search2 10 d2 miss on miss on search3 miss on this device figure 6-48. timing diagram for mixed search below block 2 winning device cmd[2] the last a-cycle cmpr[2] on b-cycles logic 0 for a-cycles for x72 and x144 logic 0 on 1st x288 a-cycle logic 1 on the |(lhi[6:0]) 0 0 lho[1:0] |(bhi[2:0]) 0 z z z z z z z 1 0 this device this device 1 0 for non-enhanced mode: cynse10512: cfg[63:0] = aaaaaaaaaaaaaaaah; cynse10256: cfg[31:0] = aaaaaaaah; CYNSE10128, cfg[15:0] = aaaah. nes = 10 (binary) in all blocks for enhanced mo de, x288 search. hlat = 000 (binary), tlsz = 10 (binary), lram = 0 (binary), ldev = 0 (binary). m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 105 of 153 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[m:0] ssf ssv ale_l search1 search2 10 10 search1 search3 a b a b a b a b a b1 b2 c1 c2 c3 c4 dq d1 d3 search2 10 d2 miss on miss on search3 miss on this device figure 6-49. timing diagram for mixed search for all except the last device in block 3 cmd[2] the last a-cycle cmpr[2] on b-cycles logic 0 for a-cycles for x72 and x144 logic 0 on 1st x288 a-cycle logic 1 on the |(lhi[6:0]) 0 0 lho[1:0] |(bhi[2:0]) 0 z z z z z z z 1 0 this device this device 1 0 for non-enhanced mode: cynse10512: cfg[63:0] = aaaaaaaaaaaaaaaah; cynse10256: cfg[31:0] = aaaaaaaah; CYNSE10128, cfg[15:0] = aaaah. nes = 10 (binary) in all blocks for enhanced mo de, x288 search. hlat = 000 (binary), tlsz = 10 (binary), lram = 0 (binary), ldev = 0 (binary). m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 106 of 153 for non-enhanced mode: cynse10512: cfg[63:0] = aaaaaaaaaaaaaaaah; cynse10256: cfg[31:0] = aaaaaaaah; CYNSE10128, cfg[15:0] = aaaah. nes = 10 (binary) in all blocks for enhanced mode, x288 search hlat = 000 (binary), tlsz = 10 (binary), lram = 1 (binary), ldev = 1 (binary). cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[m:0] ssf ssv ale_l search1 search2 10 10 search1 search3 a b a b a b a b a b1 b2 c1 c2 c3 c4 dq d1 d3 search2 10 d2 hit on some hit on some search3 hit on some figure 6-50. timing diagram for mixed search for the last device in block 3 cmd[2] the last a-cycle cmpr[2] on b-cycles logic 0 for a-cycles for x72 and x144 logic 0 on 1st x288 a-cycle logic 1 on the |(lhi[6:0]) 0 0 lho[1:0] |(bhi[2:0]) 0 0 0 1 0 device above device above 1 0 z z z z 0 0 0 z z 0 0 z z 1 1 1 0 z z 0 0 0 z z 0 0 device above m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 107 of 153 the following is the sequence of operation for a si ngle mixed-width search command (also refer to subsection 6.2, ?command bus parameters,? on page 50 ). ?cycle a: ? command bus : the host asic drives cmdv high and applies sear ch command cmd[1:0] = ?10? (binary). the cmd[2] and cmd[9] signals must be driven to lo gic 0 for the 72-bit search, but for 144-bit search, cmd[9] = 1 and cmd [2] = 0. for 288-bit search, cmd[9] is don?t ca re, whereas cmd[2] = 1 for the first ?a? cycle and 0 for the last ?a? cycle. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair for us e in this search operation. cmd[8:6] signals must be driven with the same bits that will be driven on sadr[25:23] for cynse10512, sadr[24:22] for cynse10256, sadr[23:21] for CYNSE10128 by this device if it has a hit. ? dq bus : at the same time in cycle a, dq[71:0] must be driv en with the 72-bit data to be compared. ? cycle b : ? command bus : the host asic continues to drive cmdv high and to apply search command cmd[1:0] = ?10? (binary). cmd[5:2] must now be driven by the index of the comparand regi ster pair for storing the search key presented on the dq bus during cycles a and b. cmd[8:6] sig nals must be driven with the index of t he ssr that will be us ed for storing the address of the matching entry and hit flag (see page 27 for a description of ssr[0:7]). cmd[10:9] are don?t cares for this cycl e. ? dq bus : the dq[71:0] continues to carry the search key to be compared. note . for 72-bit searches, the host asic must supply the same 72-bit data on dq[71:0] during both cycles a and b. also, the even and odd pairs of gmrs selected for the comparison must be programmed with the same value. for 144-bit, 288-bit or 576- bit searches, each 72-bit presented on each cycle a and b will to gether form the 144-bit or 28 8-bit or 576-bit search key respectively. when an n-bit search key, k, is presented on the dq bus, the entire table of n-bit ent ries is compared to the search key using the gmr and local mask bits. the gmr is selected by the gmr i ndex in the command?s cycle a. k is also stored in both even and odd comparand register pairs (selected by the comparand re gister index in command cycle b). k is compared with each entry in the table, starting at location 0. a matching entry that sa tisfies the soft priority and mini -key scheme (for enhanced mode) will be the winning entry, and its location address l will be driv en as part of the sram addr ess on the sadr[n:0] lines (see section 6.7, ?sram pio access,? on page 121 ), n = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128. note . the learn command is supported for onl y one of the blocks consisting of up to eight devices in a d epth-cascaded table of more than one block. for up to 31 devices in the table (tlsz = 10 (binary)), search latency is 6 from command to sram access cycle. in addition, ssv and ssf shift further to t he right for different values of hlat, as specified in table 6-5 . 6.5.9 mixed-size multi searches with 8 devices on tables co nfigured with different widths this subsection will cover mixed searches (72, 144, and 288) with tables of different widt hs (72, 144, 288) when multi- search is enabled. the sample operation shown is for 8-device-cascade, with devices 0 and 1 containing x72 tables (nes = 00 (binary) in all blocks), devices 2 and 3 containing x144 tables (n es = 01 (binary) in all blocks), and devices 4 to 7 containin g x288 tables (nes = 10 (binary) in all blocks). the following figures show thr ee sequential searches: first, a 72-bit search on a 72 - configured table; a 144-bit search on a 144- configured table; and a 288-bit search on a 288-configured table that each results in a hit. the hardware connection of the 8 cascaded devices is shown in figure 6-19 . a graphical representation of the tables is shown in figure 6-51 using cynse10512s as an example. note : ? when multisearch is enabled, the maximum number of devices that can be cascaded is 8 if clk2x is less than or equal to 200 mhz. the number of devices will be 4 if cl k2x operates above 200 mhz but up to 266 mhz. ? all eight devices must be programmed with the same values for tlz (?01? (binary)) and hlat (?000? (binary) in this example). only the last device in the table must be programmed with lram = 1 (binary) and ldev = 1 (binary) (device 7 in this case). all other upstream devices must be programm ed with lram = 0 (binary) and ldev = 0 (binary) (devices 0 through 6 in this case). devices 4 to 7, 128k total entries in each array devices 0 and 1, 256k total entries in each array 72 devices 2 and 3, 128k total entries in each array 144 288 nes = 00 figure 6-51. multiwidth configurations example for multisearch with cynse10512s nes = 01 nes = 10 72 144 288 array 0 array 1 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 108 of 153 ? the device receiving all the lho signals from the other devices is considered the last device. ? all the shared signals in the following timing diagrams showing tri-stated condition (?z?) indica te that, that particular devi ce is not driving the shared signals. the shared si gnals are not three-stated in a real lif e because other devices will be driving th em. ? comparing the hardware diagrams shown in figure 6-9 and figure 6-14 , enabling multisearch does not mean that a board layout change is required. the lho_1_l and lhi_1_l share the sa me pin with the full in and full out signals, which are not shown in figure 6-9 . cascading multiple devices togethe r still allow the user to configur e the devices through software to perform single-search or multisearch operations without any board change. ? one way to create many tables of different widths in a bank of nses is by having table designation bits. it is assumed that bits [71:70] for each entry will be the table designation bits. the dq[71:70] will be 00 in eac h of the two a and b cycles of the 72- bit multisearch (m-search1). dq[71:70] is 01 in each of the a and b cycles of the 144-bit multisearch (m-search2). dq[71:70] is 10 in each of the a, b, c, and d cycles of the 288 -bit multisearch (m-search3). the timing diagrams below corresponds to the hit/miss assumptions defined in table 6-12 . table 6-12. hit/ miss assumptions in multisearchmode search number #1 (x72) #2 (x144) #3 (x288) device 0 miss hit miss miss miss miss device 1 miss hit miss miss miss miss device 2 miss miss miss hit miss miss device 3 to 6 miss miss miss miss miss miss device 7 miss miss miss miss hit miss [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 109 of 153 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 nes = 00 (binary) in all blocks for enhanced mo de, x72 search. hlat = 000 (binary), tlsz = 01 (binary), lram = 0 (binary), ldev = 0 (binary). phs_l sadr[m:0] ssf ssv ale_l m-search1 m-search2 10 10 m-search1 m-search3 a b a b a b a b c1 c2 d1 d2 d3 d4 dq d1 d3 m-search2 10 d2 array 0 miss on m-search3 miss on figure 6-52. timing diagram for mixed mu ltisearch (eight devices) for device 0 cmd[2] the last a-cycle cmpr[2] on b-cycles logic 0 for a-cycles for x72 and x144 logic 0 on 1st x288 a-cycle logic 1 on the |(lhi_0[6:0]) 0 0 lho_0[1:0] &(lhi_1_l[6:0]) 1 1 lho_1_l[1:0] z z z z z z z 0 1 addr z z 0 z z z z a b d2 0 1 1 1 miss m-search1 array 1 hit both arrays both arrays b m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 110 of 153 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[m:0] ssf ssv ale_l m-search1 m-search2 10 10 m-search1 m-search3 a b a b a b a b c1 c2 d1 d2 d3 d4 dq d1 d3 m-search2 10 d2 array 0 miss on m-search3 miss on figure 6-53. timing diagra m for mixed multisearch (eig ht devices) for device 1 cmd[2] the last a-cycle cmpr[2] on b-cycles logic 0 for a-cycles for x72 and x144 logic 0 on 1st x288 a-cycle logic 1 on the |(lhi_0[6:0]) 0 0 lho_0[1:0] &(lhi_1_l[6:0]) 1 1 lho_1_l[1:0] z z z z z z z 0 1 a b d2 miss m-search1 array 1 local hit but suppressed both arrays both arrays 0 1 nes = 00 (binary) in all blocks for enhanced mode, x72 search. hlat = 000 (binary), tlsz = 01 (binary), lram = 0 (binary), ldev = 0 (binary). m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 111 of 153 nes = 01 (binary) in all blocks for enhanced mo de, x144 search. hlat = 000 (binary), tlsz = 01 (binary), lram = 0 (binary), ldev = 0 (binary). cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[m:0] ssf ssv ale_l m-search1 array 0 m-search2 10 10 m-search1 m-search3 a b a b a b a b c1 c2 d1 d2 d3 d4 dq d1 d3 m-search2 10 d2 miss on this device miss on m-search3 miss on figure 6-54. timing diagram for mixed mu ltisearch (eight devices) for device 2 cmd[2] the last a-cycle cmpr[2] on b-cycles logic 0 for a-cycles for x72 and x144 logic 0 on 1st x288 a-cycle logic 1 on the |(lhi_0[6:0]) 0 0 lho_0[1:0] &(lhi_1_l[6:0]) 1 1 lho_1_l[1:0] z z z z z z z 1 addr z z 0 z z z z a b d2 0 1 1 1 m-search1 array 1 miss on array 1, hit both arrays 0 1 this device on array 2 c m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 0 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 112 of 153 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[m:0] ssf ssv ale_l m-search1 array 0 m-search2 10 10 m-search1 m-search3 a b a b a b a b c1 c2 d1 d2 d3 d4 dq d1 d3 m-search2 10 d2 miss on this device miss on m-search3 hit on array 0 figure 6-55. timing diagram for mixed mu ltisearch (eight devices) for device 7 cmd[2] the last a-cycle cmpr[2] on b-cycles logic 0 for a-cycles for x72 and x144 logic 0 on 1st x288 a-cycle logic 1 on the |(lhi_0[6:0]) 0 0 lho_0[1:0] &(lhi_1_l[6:0]) 1 1 lho_1_l[1:0] z 0 1 addr z z a b d2 1 1 m-search1 array 1 miss on both arrays miss on array 1 0 1 this device on this device z 0 0 z z 0 0 z z 1 1 0 z z z z 0 0 0 0 d nes =10 (binary) in all blocks for enhanced mode, x288 search hlat = 000 (binary), tlsz = 01 (binary), lram = 0 (binary), ldev = 0 (binary). m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 113 of 153 the mse bit in the command register must be set high to enabl e the multisearch feature. th e same with the enhanced mode (emode) bit. the following is the sequence of operation fo r a single mixed-width search command (also refer to subsection 6.2, ?command bus parameters,? on page 50 ). ?cycle a : ? command bus : the host asic drives cmdv high and applies sear ch command cmd[1:0] = ?10? (binary). the cmd[2] and cmd[9] signals must be driven to lo gic 0 for the 72-bit search, but for 144-bit search, cmd[9] = 1 and cmd [2] = 0. for 288-bit search, cmd[9] is don?t ca re, whereas cmd[2] = 1 for the first ?a? cycle and 0 for the last ?a? cycle. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair for us e in this search operation. cmd[7:6] signals must be driven with the same bits that will be driven on sadr[24:23] for cynse10512, sadr[23:22] for cynse10256, sadr[22:21] for CYNSE10128 by this device if it has a hit. cmd[ 8] must be set high for multisearch operation. ? dq bus : at the same time in cycle a, dq[71:0] must be driv en with the 72-bit data to be compared. ? cycle b : ? command bus : the host asic continues to drive cmdv high and to apply search command cmd[1:0] = ?10? (binary). cmd[5:2] must now be driven by the index of the comparand regi ster pair for storing the search key presented on the dq bus during cycles a and b. cmd[8:6] sig nals must be driven with the index of t he ssr that will be us ed for storing the address of the matching entry and hit flag (see page 27 for a description of ssr[0:7]). cmd[10:9] are don?t cares for this cycl e. ? dq bus : the dq[71:0] continues to carry the search key to be compared. note . for 72-bit multi-searches, the host asic can provide differ ent 72-bit data on dq[71:0] on each of the a and b cycles. the even and odd pairs of gmrs selected for the comparison need not be programmed with the same value. for 144-bit, 288-bit or 576-bit searches, each 72-bit presented on each cycle a and b will together form the 144-bit or 288-bit or 576-bit search key respectively. each search key will be compared to both arra ys 0 and 1 during cycles a and b when multisearch is enabled. when an n-bit search key, k, is presented on the dq bus, both a rrays of n-bit entries are compared to the search key using the gmr and local mask bits. the gmr is selected by the gmr inde x in the command?s cycle a. k is also stored in both even and odd comparand register pairs (selected by the comparand regist er index in command cycle b). k is compared with each entry in the table, starting at location 0. a matc hing entry from each array that satisfies the soft priority and mini-key scheme will b e the winning entries, and their location addresses la and lb will be dr iven as part of the sram a ddress on the sadr[n:0] lines (see section 6.7, ?sram pio access,? on page 121 ), n = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128. note . the learn command is supported for onl y one of the blocks consisting of up to eight devices in a d epth-cascaded table of more than one block. the latency of the mu ltisearch from command to sram access cycle is 5 for a configuration of up to eight devices (tlsz = 01 (binary)). ssv and ssf also shift further to the right for different values of hlat, as specified in table 6-5 . 6.6 learn command the device contains sixteen pairs of compar and (cmpr) registers that st ore the search key as the device executes searches. on a search miss, signalled to the asic th rough the ssv and ssf signals (ssv = 1 (binary), ssf = 0 (binary)), the host asic can apply the learn command to learn the en try from a cmpr register to the next-fr ee location. however, it is recommended that the host asic first check the full signal, to determine if the dev ice is full. if the device is not full, and the search was a miss, a learn can be applied. if the device is already full, and the learn is issued, the operation will be suppressed. the learn command is a pipelined ope ration and lasts for two clk cycles. figure 6-60 , figure 6-61 and figure 6-62 show the timing diagram of learn operatio ns with the address taken from the nfa or srr register. learn operati ons with the address taken from the dq bus follow the same diagrams except that t he dq bus contains the addre ss instead of don?t cares. figure 6-61 and figure 6-62 assume that the device performing the learn operation is not the last device in the ta ble and will therefore have its lram bit set to 0. the oe_l for the devi ce with the lram bit set goes high for two cycles for each lear n (one during the sram write cycle and one during the cycle before). the sram write cycle la tency from the second cycle of the instruction is shown in table 6-13 . the learn command also generates a write cycle to the external sram (see section 6.7, ?sram pio access,? on page 121 ). note that mismatched entry-width learn operat ion is not supported. for example, the resu lt of a 72-bit search miss stored in on e of the srr registers cannot be used for a 144-bit learn operation. 6.6.1 non-enhanced mode the learn command in the non-enhanced mode supports x72 and x144 table widths. the operation uses the data stored in the user selected cmpr register for writing to an entry in the data array. non-enhanced mode learn operation ignores the dq bus and cannot perform a write to the mask arra y. the address for the target data entry is the index field of the next-free address (nfa) register. once the operation is completed the nfa register?s index field is updated with next highest priority free entry in the data arr ay. the lsb of each x72 entry is treated as a valid bit and used to indicate whether that entry is free (=0 (binary)) or not (=1 (b inary)). for a 144-bit entry, bit [72] and bit[0] must be set to the same value. [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 114 of 153 note that learn command for x144 entry width in non-enhanced c an only be issued when all the tables in the device is of x144 table width. 6.6.2 enhanced mode the learn command in the enhanced mode supports all table wid ths (x72, x144, x288 and x576). the user can select whether the data stored in the user selected cmpr r egister or the data presented in the dq bus be used for the learn operation. the use r can also select to write to an entry in ei ther the data or mask array. the address fo r the target entry is the index field of t he user- selected search result register (srr). each srr is one-to-one associated to a comparand (cmpr) register. so the selection of the srr is accomplished by selecting the corresponding (cmpr) register. the srr register is updated after a search operation. only the lsb of each entry is us ed, regardless of width, to indicate whet her that entry is free (=0 (binary)) or not (=1 (binary)). cycle learn clk2x cmdv cmd[1:0] dq sadr[m:0] cmd[5:2] we_l oe_l a1 x72 tlsz = 00 (binary), lram = 1 (binary), ldev = 1 (binary). 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l 1 1 0 0 0 0 0 ssv ssf 10 1 1 ce_l figure 6-56. timing diagram of 72-bit learn from dq bus and cmpr registers (one device) m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 ale_l 1 0 learn cmd[10] cmd[9] cmpr b learn from dq learn from cmpr learn data learn mask cmpr a [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 115 of 153 cycle clk2x cmdv cmd[1:0] dq sadr[m:0] cmd[5:2] we_l oe_l a1 tlsz = 10 (binary), lram = 1 (binary), ldev = 1 (binary). 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l 1 z 0 0 0 ssv ssf ce_l figure 6-57. timing diagram of 288-bit learn from dq bus and cmpr registers (one device) m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 ale_l 288-bit learn cmd[10] cmd[9] learn from dq learn from cmpr learn data learn mask cmpr x1 d0 d1 d2 d3 288-bit learn cmpr x2 cmpr y1 cmpr y2 1 1 0 1 1 0 1 1 0 0 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 116 of 153 cycle clk2x cmdv cmd[1:0] dq sadr[m:0] cmd[5:2] we_l oe_l a1 tlsz = 10 (binary), lram = 1 (binary), ldev = 1 (binary). 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l 1 z 0 0 0 ssv ssf ce_l figure 6-58. timing diagram of 576- bit learn from dq bus (one device) m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 ale_l cmd[10] cmd[9] learn from dq learn data cmpr x1 d0 d1 d2 d3 cmpr x2 1 1 0 1 1 0 1 1 0 0 576-bit learn cmpr cmpr x3 x4 d4 d5 d6 d7 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 117 of 153 6.6.3 learn operation on depth-cascaded table when all entries in a device are occupied, the device asserts fulo to inform the downstream devices that it is full. the result of this communication between depth-cascaded devices determines the global full signal for the entire table. the full signal in the last device determines the fullness of the depth-cascaded table. in a depth-cascaded table, only a single device will learn the en try through the application of a learn instruction. the determ i- nation as to which device will learn is based on the fuli and fulo signals between the devices. the first non-full device learn s the entry by storing the content of the selected cmpr register to the location po inted to by the nfa or srr register. the global full signal indicates to the table controller (the ho st asic) that all entries within a block are occupied and that no more entries can be learned. the ayama 10000 device updates the signal after each write or learn command to a data array. cycle clk2x cmdv cmd[1:0] dq sadr[m:0] cmd[5:2] we_l oe_l tlsz = 10 (binary), lram = 1 (binary), ldev = 1 (binary). 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l 0 0 ssv ssf ce_l figure 6-59. timing diagram of 576-bit learn from cmpr register (one device) m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 ale_l cmd[10] cmd[9] learn from cmpr learn mask cmpr x1 cmpr x2 576-bit learn cmpr x3 cmpr x4 1 1 1 1 1 1 0 0 z [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 118 of 153 . cycle learn1 clk2x cmdv cmd[1:0] dq sadr[m:0] cmd[10:2] x we_l oe_l a1 a2 x xxx x tlsz = 00 (binary), lram = 1 (binary), ldev = 1 (binary). 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 x x x 1a 1b comp1 comp2 x phs_l 1 1 z z 0 0 0 0 0 0 0 ssv ssf 1 0 1 1 ce_l learn2 figure 6-60. timing diagram of learn (tlsz = 00 (binary), ldev = 1 (binary)) m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 ale_l 1 0 0 1 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 119 of 153 cycle learn1 learn2 clk2x cmdv cmd[1:0] dq sadr[m:0] ce_l cmd[10:2] we_l oe_l a1 a2 x xxx x tlsz = 01 (binary), lram = 0 (binary), ldev = 0 (binary). 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 x 1a1b comp1 comp2 x phs_l z z z z z z z 0 0 z z ssv ssf z 00 x figure 6-61. timing diagram of learn (except on the last device [tlsz = 01 (binary)]) m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 ale_l z 0 0 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 120 of 153 the learn operation lasts two clk cycles. the sequence of operation is as follows. ? cycle 1a : the host asic applies the learn instruction on cmd[1:0] us ing cmdv = 1 (binary). the cmd[5:2] fiel d specifies the index of the comparand register pair that will be written in the data array in th e 144-bit-configured table. for a learn in a 72-bit-configured table, the even-numbered comparand specified by this index will be written. cmd[8:6] carries the bits that will be driven on sadr[25:23] for cynse 10512, sadr[24:22] for cynse10256, sadr[ 23:21] for CYNSE10128 in the sram write cycle. ? cycle 1b : the host asic continues to drive cmdv to 1 (binary), cm d[1:0] to 11 (binary), and cmd[5:2] with the comparand pair index. cmd[6] must be set to 0 if the learn is being perfo rmed on a 72-bit-configured table, and to 1 if the learn is being performed on a 144-bit-configured table. ? cycle 2 : the host asic drives cmdv to 0. at the end of cycle 2, a new instruction can begin. sram write la tency is the same as the search to the sram read cycle. it is measured from the second cycl e of the learn instruction. table 6-13. sram write cycle latency fr om second cycle of learn instruction number of devices latency in clk cycles 1 (tlsz = 00 (binary)) 4 1?8 (tlsz = 01 (binary)) 5 1?31 (tlsz = 10 (binary)) 6 cycle learn1 learn2 clk2x cmdv cmd[1:0] dq sadr[m:0] ce_l cmd[10:2] x we_l oe_l x xxx x tlsz = 01 (binary), lram = 1 (binary), ldev = 1 (binary). 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 x x x 1a 1b comp1 comp2 x phs_l 1 1 z z z z z 0 zz zz 0 0 ssv ssf 1 1 1 0 z 1 1 figure 6-62. timing diagram of learn on device number 7 (tlsz = 01 (binary)) m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 ale_l 1 zz1 1 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 121 of 153 6.7 sram pio access sram read enables read access to the off-chip sram containing associative data. the latency from the issuance of the read instruction to the appearance of the address on the sram bus is the same as the search instruction latency, and will depend on the value programmed for the tlsz parameter in the device co nfiguration register. the latency of the ack from the read instruction is the same as that from t he search instruction to the sram address latency, plus the hlat programmed in the configuration register. note . sram read is a blocking operation?no new instru ction can begin until the ack is returned by the selected device performing the access. sram write enables write access to the off-chip sram containi ng associative data. the latency from the second cycle of the write instruction to the appearance of the a ddress on the sram bus is the same as th e search instruction latency, and will depe nd on the tlsz value parameter programmed in the device configuration register. note : sram write is a pipelined operation?new instruction can begin right after the previous command has ended. 6.7.1 sram read with a table of one device sram read enables read access to the off-chip sram containing associative data. the latency from the issuance of the read instruction to the appearance of the address on the sram bus is the same as search instruction latency, and will depend on the tlsz value parameter programmed into the device configuration r egister. ack latency from the read instruction is the same as that from the search instruction to the sr am address, plus the hlat programmed in the configuration register. the following explains the sram read operation in a table with only one devi ce that has the following parameters: tlsz = 00 (binary), hlat = 000 (binary), lram = 1 (binary), and ldev = 1 (binary). figure 6-63 shows the associated timing diagram. for the following description, the selected device refers to the only device in the table because it is the only device to be accessed. ? cycle 1a : the host asic applies the read instruction on cmd[1:0] usi ng cmdv = 1 (binary). the dq bus supplies the address, with dq[20:19] set to 10 (binary), to se lect the sram address. the host asic se lects the device for which id[4:0] matches the dq[25:21] lines. during this cycle, the host asic al so supplies sadr[25:23] for cynse10512, sadr[24:22] for cynse10256, sadr[23:21] fo r CYNSE10128 on cmd[8:6]. ? cycle 1b : the host asic continues to apply the read instruction on cmd[1:0] using cmdv = 1 (binary). the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. ? cycle 2 : the host asic floats dq[71:0] to a three-state condition. ? cycle 3 : the host asic keeps dq[71:0] in a three-state condition. ? cycle 4 : the selected device starts to drive dq[7 1:0] and drives ack from high-z to low. ? cycle 5 : the selected device drives the read address on sadr[n:0] lines (n = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128) and drives ack high, ce_l low, and ale_l low. ? cycle 6 : the selected device drives ce_l high, ale_l high, the sa dr bus, the dq bus in a three-state condition, and ack low. at the end of cycle 6, the selected dev ice floats ack in a three-state cond ition, and a new command can begin. [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 122 of 153 6.7.2 sram read with a table of up to eight devices the following explains the sram read operation completed through a table of up to eight devices using the following parameter: tlsz = 01 (binary). figure 6-64 diagrams a block of eight devices. the follo wing assumes that sram access is successfully achieved through ayama 10000 device number 0. figure 6-65 and figure 6-66 show timing diagrams for device number 0 and device number 7, respectively. ? cycle 1a : the host asic applies the read instru ction on cmd[1:0] using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to 10, to select the sram address. the host asic selects the de vice for which id[4:0] matches the dq[25:21] lines. during this cycle the host asic also supplies sadr[25:23] for cynse10512, sadr[24:22] for cynse10256, sadr[23:21] for cynse1 0128 on cmd[8:6]. ? cycle 1b : the host asic continues to apply the read instruction on cmd[1:0], using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to 10, to select the sram address. ? cycle 2 : the host asic floats dq[71:0] to a three-state condition. ? cycle 3 : the host asic keeps dq[71:0] in a three-state condition. ? cycle 4 : the selected device starts to drive dq[71:0]. ? cycle 5 : the selected device continues to drive dq[7 1:0] and drives ack from high-z to low. ? cycle 6 : the selected device drives the read address on sadr[n:0] lines (n = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128) and drives ack high, ce_l low, we_l high, and ale_l low. ? cycle 7 : the selected device drives ce_l, ale_l, we_l, and the dq bus in a three-state condition. it continues to drive ack low. at the end of cycle 7, the selected device floats ack in a three-state condition. a new command can begin. cycle clk2x dq read address ack oe_l we_l ale_l sadr address 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 tlsz = 00 (binary), hlat = 000 (binary), lram = 1 (binary), ldev = 1 (binary) phs_l cmd[10:2] a b z z 0 1 0 z z 0 0 1 z 1 z 1 ssv 0 0 ssf ce_l 1 0 1 dq driven by ayama 10000 cmdv cmd[1:0] figure 6-63. sram read access (tlsz = 00 (binary), hl at = 000 (binary), lram = 1 (binary), ldev = 1 (binary)) [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 123 of 153 lho[0] 6543210 lhi lho[0] 65 32 10 lhi lho[1] 6543 210 lhi lho[0] 654321 0 lhi lho[0] 654 3210 lhi lho[0] 65 4 3210 lhi lho[0] 654 32 10 lhi bho[0] 65 4 3 210 lhi lho[0] lhi lhi lhi lho[1] lho[1] lho[1] bho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[71:0] sram lho[1] lho[0] ayama 10000 #0 ayama 10000 #1 ayama 10000 #2 ayama 10000 #3 ayama 10000 #4 ayama 10000 #5 ayama 10000 #6 ayama 10000 #7 4 bho[2] bho[2] cmdv cmd[10:0] ssf, ssv figure 6-64. hardware diagram of a block of eight devices [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 124 of 153 cycle clk2x cmdv cmd[1:0] dq address oe_l we_l ce_l sadr address 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 tlsz = 01 (binary) , hlat = 000 (binary) , lram = 0 (binary) , ldev = 0 (binary) phs_l cmd[10:2] a z z z z 0 z z z ssv z ssf ale_l z 0 z z 0 0 1 z z 1 cyc l e 7 dq driven by selected ayama 10000 figure 6-65. sram read of device #0 in a block of eight devices ack b read [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 125 of 153 6.7.3 sram read with a table of up to 31 devices the following explains the sram read operation accomplished through a table of up to 31 devices, using the following parameter: tlsz = 10 (binary). the hardware diagram is shown in figure 6-67 . the following assumes that sram access is being accom- plished through ayama 10000 device number 0, an d that device number 0 is the selected device. figure 6-68 and figure 6-69 show the timing diagrams for device numbe r 0 and device number 30, respectively. ? cycle 1a : the host asic applies the read instru ction to cmd[1:0] using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to 10, to select the sram address. the host asic selects the devi ce for which the id[4:0] matches the dq[25:21] lines. during this cycle, the host asic also supplies sad r[25:23] for cynse10512, sa dr[24:22] for cynse10256, sadr[23:21] for cynse1 0128 on cmd[8:6]. ? cycle 1b : the host asic continues to apply the read instruction to cmd[1:0], using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to 10, to select the sram address. ? cycle 2 : the host asic floats dq[71:0] to a three-state condition. ? cycle 3 : the host asic keeps dq[71:0] in a three-state condition. ? cycle 4 : the selected device starts to drive dq[71:0]. ? cycles 5 to 6 : the selected de vice continues to drive dq[71:0]. ? cycle 7 : the selected device continues to drive dq [71:0], and drives an sram read cycle. ? cycle 8 : the selected device drives ack from z to low. ? cycle 9 : the selected device drives ack to high. ? cycle 10 : the selected device drives ack from high to low. at the end of cycle 10, the selected device floats ack to high-z and a new command can begin. cycle clk2x cmdv cmd[1:0] dq read address oe_l we_l ce_l sadr 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 tlsz = 01 (binary) , hlat = 000 (binary) , lram = 1 (binary) , ldev = 1 (binary) phs_l cmd[10:2] a b z 0 1 z z 1 1 ssv z ssf ale_l 1 z 1 z z z ack z 1 figure 6-66. sram read timing of d evice #7 in a block of eight devices [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 126 of 153 bho[2] block of 8 ayama 10000s block 0 bho[1] bho[0] bhi[2] bhi[1] bhi[0] bhi[2] block of 7 ayama 10000s block 3 bhi[1] bhi[0] gnd bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] gnd bhi[2] bhi[1] bhi[0] gnd block of 8 ayama 10000s block 1 block of 8 ayama 10000s block 2 dq[71:0] sram bho[2] bho[2] bho[1] bho[1] bho[0] bho[0] cmd[10:0], cmdv ssf, ssv (devices 0?7) (devices 8?15) (devices 16?23) (devices 24?30) figure 6-67. hardware diagram of 31 devices using four blocks cycle clk2x ce_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[m:0] ssf ssv z z z z cmdv cmd[1:0] cmd[10:2] 00 read a b address dq address 0 z z 1 we_l oe_l z ale_l z 0 z z z z z 1 0 0 ack dq driven by the selected ayama 10000 tlsz = 10 (binary), hlat = 010 (binary), lram = 0 (binary), ldev = 0 (binary) figure 6-68. sram read of device #0 in a bank of 31 devices m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 127 of 153 6.7.4 sram write with a table of one device sram write enables write access to the off- chip sram containing associative data. the latency from the second cycle of the write instruction to the appearance of the address on the sram bus is the same as search instruction latency, and will depend on the tlsz value parameter programmed in the device configur ation register. the following explains the sram write operation accomplished through a table of only one device with the following parameters: tlsz = 00 (binary), hlat = 000 (binary), lram = 1 (binary), and ldev = 1 (binary). figure 6-70 shows the timing diagram. for the follo wing description, the selected device refers to the only device in the table because it is the only device that will be accessed. ? cycle 1a : the host asic applies the write instru ction on cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. the host asic selects the device for which th e id[4:0] matches the dq[25:21] lines. the host asic also supplies sadr[25:23] for cyn se10512, sadr[24:22] for cynse10256, sadr[23:21] for CYNSE10128 on cmd[8:6] in this cycle. note . cmd[2] must be set to 0 for sram writ e because burst writes into the sram are not supported. ? cycle 1b : the host asic continues to apply the write instruction on cmd[ 1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. note . cmd[2] must be set to 0 for sram write because burst writes into the sram are not supported. ? cycle 2 and cycle 3 : wait states. data not used by nse. at the end of cycle 3, a new command can begi n. the write is a pipelined operation; the write cycle appears at the sram bus, however, with the same latency as the se arch instruction, as measured from the second cycle of the write command. cycle clk2x ce_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[m:0] ssf ssv 1 0 0 cmdv cmd[1:0] cmd[10:2] 00 read a b address dq z 1 we_l oe_l 0 ale_l 1 z 1 z ack z 1 1 z tlsz = 10 (binary), hlat = 010 (binary), lram = 1 (binary), ldev = 1 (binary) figure 6-69. sram read of device #0 in a bank of 31 devices m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 128 of 153 cycle clk2x cmdv cmd[1:0] dq write address ack oe_l we_l ale_l sadr 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 tlsz = 00 (binary), hlat = 000 (binary), lram = 1 (binary), ldev = 1 (binary) phs_l cmd[10:2] a b x z ssv 0 0 ssf ce_l figure 6-70. sram write access (tlsz = 00 (binary), hlat = 000 (binary), lram = 1 (binary), ldev = 1 (binary)) address 0 z 1 1 0 1 0 1 0 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 129 of 153 6.7.5 sram write with a table of up to eight devices the following explains the sram write operation accomplished th rough a table(s) of up to eight devices with the following parameters (tlsz = 01 (binary)). the hardware diagram for this table is shown in figure 6-71 . the following assumes that sram access is achieved through ayama 10000 device number 0. figure 6-72 and figure 6-73 show the timing diagram for device number 0 and device number 7, respectively. ? cycle 1a : the host asic applies the write instru ction on cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. the host asic selects the device for which th e id[4:0] matches the dq[25:21] lines. the host asic also supplies sadr[25:23] for cyn se10512, sadr[24:22] for cynse10256, sadr[23:21] for CYNSE10128 on cmd[8:6] in this cycle. note . cmd[2] must be set to 0 for sram writ e because burst writes into the sram are not supported. lho[0] 6543210 lhi lho[0] 65 32 10 lhi lho[1] 6543 210 lhi lho[0] 654321 0 lhi lho[0] 654 3210 lhi lho[0] 65 4 3210 lhi lho[0] 654 32 10 lhi bho[0] 65 4 3 210 lhi lho[0] lhi lhi lhi lho[1] lho[1] lho[1] bho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[71:0] sram lho[1] lho[0] ayama 10000 #0 ayama 10000 #1 ayama 10000 #2 ayama 10000 #3 ayama 10000 #4 ayama 10000 #5 ayama 10000 #6 ayama 10000 #7 4 bho[2] bho[2] cmdv cmd[10:0] ssf, ssv figure 6-71. hardware diagram of a block of eight devices [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 130 of 153 ? cycle 1b : the host asic continues to apply the write instruction on cmd[ 1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. note . cmd[2] must be set to 0 for sram write because burst writes into the sram are not supported. ? cycle 2 : the host asic continues to drive dq [71:0]. the data in this cycle is not used by the ayama 10000 device. ? cycle 3 : the host asic continues to drive dq [71:0]. the data in this cycle is not used by the ayama 10000 device. at the end of cycle 3, a new command can begin. write is a pi pelined operation, but the writ e cycle appears at the sram bus with the same latency as that of a se arch instruction, as me asured from the second cycle of the write command. cycle clk2x ce_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[m:0] ssf ssv z z cmdv cmd[1:0] cmd[10:2] 01 write a b address dq we_l oe_l z ale_l z ack x x z tlsz = 01 (binary), hlat = xxx, lram = 0 (binary), ldev = 0 (binary) figure 6-72. sram write of devi ce #0 in a block of eight devices m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 z address 0 z z z 0 0 z z z z [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 131 of 153 6.7.6 sram write with table(s) consisting of up to 31 devices the following explains the sram write operation accomplished thr ough a table of up to 31 devices with the following parameter: tlsz = 10 (binary). the hardware diagram is shown in figure 6-74 . the following assumes that sram access is accomplished through ayama 10000 device number 0?the selected device. figure 6-75 and figure 6-76 show timing diagrams for device number 0 and device number 30, respectively. ? cycle 1a : the host asic applies the write instru ction on cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. the host asic selects the device for which th e id[4:0] matches the dq[25:21] lines. the host asic also supplies sadr[25:23] for cyn se10512, sadr[24:22] for cynse10256, sadr[23:21] for CYNSE10128 on cmd[8:6] in this cycle. note . cmd[2] must be set to 0 for sram write because burst writes into the sram are not supported. ? cycle 1b : the host asic continues to apply the write instruction on cmd[ 1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. note . cmd[2] must be set to 0 for sram write because burst writes into the sram are not supported. ? cycle 2 : the host asic continues to drive dq [71:0]. the data in this cycle is not used by the ayama 10000 device. ? cycle 3 : the host asic continues to drive dq [71:0]. the data in this cycle is not used by the ayama 10000 device. at the end of cycle 3, a new co mmand can begin. the write is a pipelined operation, but the write cycle appears at the sram bus with the same latency as that of a search instructi on, as measured from the se cond cycle of the write command. cycle clk2x ce_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[m:0] ssf ssv 0 0 cmdv cmd[1:0] cmd[10:2] 01 write a b address dq we_l oe_l ale_l z ack x x tlsz = 01 (binary), hlat = xxx, lram = 1 (binary), ldev = 1 (binary) figure 6-73. sram write timing of device #7 in block of eight devices m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 1 z 0 z 1 0 1 1 z 1 1 z 1 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 132 of 153 bho[2] block of 8 ayama 10000s block 0 bho[1] bho[0] bhi[2] bhi[1] bhi[0] bhi[2] block of 7 ayama 10000s block 3 bhi[1] bhi[0] gnd bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] gnd bhi[2] bhi[1] bhi[0] gnd block of 8 ayama 10000s block 1 block of 8 ayama 10000s block 2 dq[71:0] sram bho[2] bho[2] bho[1] bho[1] bho[0] bho[0] cmd[10:0], cmdv ssf, ssv (devices 0?7) (devices 8?15) (devices 16?23) (devices 24?30) figure 6-74. table of 31 devices (four blocks) cycle clk2x ce_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[m:0] ssf ssv z z cmdv cmd[1:0] cmd[10:2] 01 write a b address dq we_l oe_l z ale_l z ack x x z tlsz = 10 (binary), hlat = xxx, lr am = 0 (binary), ldev = 0 (binary) figure 6-75. sram write of device #0 in bank of 31 devices m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 z address 0 z z z z 0 z 0 z z [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 133 of 153 6.8 timing sequences for back-to-back operations table 6-14 shows the idle cycle requirements betwe en operations. the oper ations in the second co lumn repres ent operations already performed, and the operations in the first row are those we would like to perform next. example calculations : 1. read after write: the wr ite takes two 2 cycles, and one 1 id le cycle is required. thus if the write is issued in cycle 1, the read cannot be issued until cycle 4. note, all cycles after an sram read or an nse read (blocking) operation ar e considered blocked until the ack signal is returned. 2. learn from srr after search x288, with tlsz=10 (binary): the se arch takes 2 cycles, and (2+tlsz) idle cycles are required. thus if the search is issued in cycl e 1, the learn cannot be issued until cycle 7. table 6-14. required idle cycles between commands notes: 15. when the register being read is ssr/srr and it matches the ta rget location of the previous search, a read operation cannot b e issued for 2+tlsz idle cycles to avoid reading the old value. otherwise there is no idle cycle requirement. 16. in non-enhanced mode there is no idle cycle requirement. in enhanced mode, an srr is updated on a search miss and is used as the address for the learn. must wait for 2+tlsz cycles after the last search, before issuing a subsequent learn that uses the same srr as the last search. 17. the sram operation needs to insert idle cycles to avoid sadr bus contention with previous search. 18. in non-enhanced mode, a write operation updat es the nfa register used for learn operat ion. must wait for 1+tlsz cycles befor e issuing learn to avoid learning with the old nfa value. 19. if the learn is issued 2+tlsz after the corresponding search that updated the srr, the learn will be issued before the searc h result or the updated full signal is returned. if the search resulted in a hit, the learn will be suppressed. if there was a miss, but the device is alrea dy full, the learn will also be suppressed. figure 6-76. sram write through device #30 in bank of 31 devices 0 0 z cycle clk2x ce_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[m:0] ssf ssv 1 cmdv cmd[1:0] cmd[10:2] 01 write a b address dq z we_l oe_l 0 ale_l z ack x x 1 1 1 z 1 1 z 1 tlsz = 10 (binary), hlat = xxx, lr am = 1 (binary), ldev = 1 (binary) m = 25 for cynse10512, 24 for cynse10256, 23 for CYNSE10128 0 # of cycles operations search read write learn sram 1 cycle read 5 5 5 5 5 2 cycles write 1 1 1 1 / 1+tlsz 18 1 x72/x144 = 1 cycle x288 = 2 cycles x576 = 4 cycles learn 1 1 1 1 1 1 cycle sram read 5+tlsz+hlat 5+tlsz+hlat 5+tlsz+hlat 5+tlsz+hlat 5+tlsz+hlat 2 cycles sram write 1 1 1 1 1 search x72/x144 = 1 cycle x288 = 2 cycles x576 = 4 cycles tlsz / 2+tlsz 17 no w ait no w ait / 2+tlsz 15 no w ait no wait / 2+tlsz 16,19 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 134 of 153 6.9 full signal timing diagram full indicates when the array (non-enhanced mode) or selected blocks (enhanced mode) is full. in non-enhanced mode, full is valid four clk1x cycles after the command is issued, regardl ess of tlsz and hlat. at all other times, full maintains its value until another operation changes it. in enhanced mode, full is valid when ssv is high. figure 6-77 is a timing diagram of the full signal in enhanced (top) and non-enhanced (bottom) modes. search2 m-search2 10 10 10 10 a b a b a b a b 10 a b cycle clk2x cmdv cmd[1:0] dq cmd[10:2] 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l ssf ssv search1 m-search1 figure 6-77. timing diagram for full signal (tlsz = 10) m-search3 cycle 11 cycle 12 0 0 1 a b c e df g h full 0 0 0 0 0 0 0 0 1 111 1 1 minikey-enabled tables in search1 and m-search2b are full search1 table is full search2 table is not full m-search1 array 0 and 1 tables are not full m-search2 array 0 table is not full, array 1 is full m-search3 tables are not full search2 search4 x72 x72 x144 x72 a b a b a b a b x144 a b cycle clk2x cmdv cmd[1:0] dq cmd[10:2] 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l ssf ssv search1 search3 search5 cycle 11 cycle 12 0 0 1 a b full 0 0 0 e c d f g 72-bit configured portion of the array is full 144-bit configured portion of the array is not full searches 1 and 2 shows x72 table full search 3 shows x144 table not full search 4 shows x72 table full search 5 shows x144 table not full 0 0 0 0 0 1 1 1 1 1 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 135 of 153 7.0 jtag (ieee 1149.1) the ayama 10000 device supports the test access port and boundary scan architectu re as specified in ieee jtag standard number 1149.1. the pin interface to the chip consists of five signals with the standard definitions: tck, tms, tdi, tdo, and trst_l. table 7-1 describes the operations that the te st access port controller supports, and ta ble 7 -2 describes the tap device id register. jtag can also be reset by driving tms high, and then holding it for three (3) tck rising edges. note . to disable jtag functionality, connec t the tck, tms, and tdi pins to v ddq through pull-resistors and hold trst_l low. table 7-1. supported operations instruction type description sample/preload mandatory sample/preload . this operation loads the values of signals going to and from i/o pins into the boundary scan shift register to provide a snapshot of the normal functional operation. extest mandatory external test . this operation uses boundary scan values shifted in from the tap to test connectivity external to the device. bypass mandatory bypass . this operation bypasses the device in a jt ag chain by loading a single bit shift register between tdi and tdo and provides a minimum-length serial path when no test operation is required. idcode optional device jtag id code . this operation selects the jtag identification register and output the idcode field serially through tdo. clamp optional output clamp . this operation drives preset values onto the outputs of the device. highz optional high-z output . this operation sets the device output signals in high impedance state. table 7-2. tap device id register field range initial value description revision [31:28] 0001 revision number . this is the current device revision number. numbers start from one and increment by o ne for each revision of the device. part number [27:12] 0000 0000 0001 0100 part number . this is the part number for CYNSE10128. 0000 0000 0001 0101 this is the part number for cynse10256. 0000 0000 0001 0110 this is the part number for cynse10512. mfid [11:1] 000_1101_1100 manufacturer id . this field is the same as the manufacturer id used in the tap controller. lsb [0] 1 least significant bit . [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 136 of 153 8.0 power consumption figure 8-1 depicts the power consumption of ayama 10000 devices based on 80% searches, 50% i/o switching, 10-pf output load, 1.5v hstlii vddq_asic/v ddq_sram, and 1.2v vdd. the power data is wit h all the blocks in the device active. a device that operates in enhanced mode and ut ilizes mini-key may have lower power c onsumption depending on the configuration. note: these values were determined through our power estimation model. please contact cypress to get an application specific power estimation. ayama10000 typical power consumption 0 2 4 6 8 10 12 14 16 18 20 25 50 83 100 133 operating frequency (mhz) power (watts) ayama10512 ayama10256 ayama10128 figure 8-1. typical power consumption of ayama 10000 [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 137 of 153 9.0 electrical specifications maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) storage temperature: ?65c to +125c ambient temperature with power applied: ?55c to +112c (q ja = 1.2 c/w) maximum junction temperature: 125c static discharge voltage (per jedec eia./jesd22-a114a): >2000v latch-up current: > 500 ma table 9-1. dc electrical char acteristics for ayama 10000 parameter description conditions v ddq = 1.5v v ddq = 1.8v v ddq = 2.5v unit min. max. min. max. min. max. i li input leakage current v ddq = v ddq max., v in = 0 to v ddq max. ?10 10 ?10 10 ?10 10 a i lo output leakage current [25] v ddq = v ddq max., v in = 0 to v ddq max. ?10 10 ?10 10 ?10 10 a v il input low voltage [21] ?0.3 v ref ? 0.1 -0.3 0.35 v ddq ?0.3 0.7 v v ih input high voltage [20] v ref + 0.1 v ddq + 0.3 0.65 v ddq v ddq + 0.3 1.7 v ddq + 0.3 v v ol output low voltage v ddq = v ddq min., i ol = 2 ma 0.40.450.7v v oh output high voltage v ddq = v ddq min., i oh = 2 ma v ddq ? 0.4 v ddq ? 0.45 1.7 v i cc cynse10000 operating current the operating current for nse devices is highly application dependent, and can vary widely due to a number of system configur ations. please contact cypress and provide system characteristics to receiv e application specific values. parameter description max. unit c in [22] input capacitance 6 / 12 [24] pf c out [23] output capacitance 6 pf table 9-2. operating conditions for ayama 10000 parameter description min. typ. max. unit v ddq = 2.5v operating voltage for i/o (2.5v lvcmos) 2.3 2.5 2.7 v v ddq = 1.8v operating voltage for i/o (1.8v lvcmos) 1.65 1.8 1.95 v v ddq = 1.5v operating voltage for i/o (hstli/ii) 1.4 1.5 1.6 v v ref reference voltage for i/o (hstli/ii) 0.68 0.75 0.9 v v dd operating supply voltage 1.14 1.2 1.26 v t a ambient operating temperature (c) 0 70 c ambient operating temperature (i) ?40 85 c notes: 20. maximum allowable applies to overshoot only. 21. minimum allowable applies to undershoot only. 22. f = 1 mhz, v in = 0 v. 23. f = 1 mhz, v out = 0 v. 24. cmd bus signals has an input capacitance of 12pf, v ref 30pf, and all others 6pf 25. output leakage current does not cover cascade (lho , bho, fulo) signals because these are always driven and are not measurable [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 138 of 153 10.0 ac timing parameters, waveforms and test conditions 10.1 ac timing parameters a nd waveforms with clk2x table 10-1. ac timing parameters with clk2x parameter description ayama 10000- 083 ayama 10000- 100 ayama 10000- 133 unit min. max. min. max. min. max. f clock clk2x frequency 100 166 100 200 100 266 mhz t lock pll lock time 0.5 0.5 0.5 ms t ckhi clk2x high pulse [23] 2.4 2.0 1.5 ns t cklo clk2x low pulse [23] 2.4 2.0 1.5 ns t isch input set-up time to clk2x rising edge [23] 1.8 1.5 1.0 ns t ihch input hold time to clk2x rising edge [23] 0.6 0.5 0.3 ns t icsch cascaded input set-up time to clk2x rising edge [24, 27] t icsch_hit lhi, bhi signals 4.5 4 3.5 ns t icsch_ful fuli signals 1.8 1.5 1 ns t ichch cascaded input hold time to clk2x rising edge [24, 27] t ichch_hit lhi, bhi signals 0 0 0 ns t ichch_ful fuli signals 0.8 0.7 0.5 ns t ckhov rising edge of clk2x to cascade output valid [27, 28] t ckhov_hit lho, bho signals 3.9 3.4 2.5 ns t ckhov_ful fulo signals 7 6.5 6 ns t ckcoh rising edge of clk2x to cascade output invalid (output hold) [30] t ckcoh_hit lho, bho signals 0.75 0.75 0.75 ns t ckcoh_ful fulo signals 1.2 1.2 1 ns t ckhovfe rising edge of clk2x to full signal valid (enhanced mode) 3.2 3 2.5 ns t ckhov_fne rising edge of clk2x to full signal valid (non- enhanced mode) 76.56ns t ckcohfe rising edge of clk2x to full invalid (enhanced mode) [30] 0.75 0.75 0.75 ns t ckcoh_fne rising edge of clk2x to full invalid (non- enhanced mode) [30] 1.2 1.2 1 ns t ckhdv rising edge of clk2x to dq valid [26] 3.5 3.0 2.5 ns t ckhdz rising edge of clk2x to dq high-z [26, 30] 0.51.80.51.80.51.8ns t ckhsv rising edge of clk2x to sram bus valid [26] 3.5 3.0 2.5 ns t ckhshz rising edge of clk2x to sram bus high-z [26, 30] 0.51.80.51.80.51.8ns t ckhslz rising edge of clk2x to sram bus low-z [26, 30] 2.2 1.9 1.9 ns t oh rising edge of clk2x to dq or sram bus invalid (output hold) 0.5 0.5 0.75 ns t rstl minimum low pulse width for rst_l 100 100 100 us notes: 26. values are based on 50% signal levels. 27. values are based on 50% signal levels and a 50%/50% duty cycle of clk1x/clk2x. 28. based on an ac load of 6 pf. 29. cascade signals only transition on clk2x cycle a rising edge 30. based on an ac load of 30 pf. this parameter is guaranteed by design and is not production tested. [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 139 of 153 phs_l signal signal signal signal group 2 group 3 group 5 group 4 t ihch t isch t icsch* t ihch signal group 1a: dq, cmd signal group 1b: cmdv signal group 2: lhi, bhi, fuli signal group 3: lho, bho, fulo, full (non-enhanced mode) signal group 4: sadr, ce_l, oe_l, we_l, ale_l, ssf, ssv signal group 5: dq, ack, eot, par, multi_hit, full (enhanced mode) t ckhov* t ckhov* t ckhdz t ckhdv, t ckhovfe t ckhshz t ckhslz t ckhsv clk2x signal group 1a t isch t ihch t isch t ichch* figure 10-1. ac timing wave forms with clk2x t ihch signal group 1b t isch signal group 4 t ckhshz t ckhslz t ckhsv (multisearch) t ckhsv t oh [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 140 of 153 10.2 ac timing parameters a nd waveforms with clk1x table 10-2. ac timing parameters with clk1x parameter description ayama 10000- 083 ayama 10000- 100 ayama 10000- 133 unit min. max. min. max. min. max. f clock clk1x frequency 50 83 50 100 50 133 mhz t lock pll lock time 0.5 0.5 0.5 ms t ckhi clk1x high pulse; worst-case duty cycle [23] 5.4 4.5 3.4 ns t cklo clk1x low pulse; wo rst-case duty cycle [23] 5.4 4.5 3.4 ns t isch input set-up time to clk1x edge [23] 1.8 1.5 1.0 ns t ihch input hold time to clk1x edge [23] 0.6 0.5 0.3 ns t icsch cascaded input set-up time to clk1x rising edge [24, 27] t icsch_hit lhi, bhi signals 4.5 4 3.5 ns t icsch_ful fuli signals 1.8 1.5 1 ns t ichch cascaded input hold time to clk1x rising edge [24, 27] t ichch_hit lhi, bhi signals 0 0 0 ns t ichch_ful fuli signals 0.8 0.7 0.5 ns t ckhov edge of clk1x to cascade output valid [27, 28] t ckhov_hit lho, bho signals 3.9 3.4 2.5 ns t ckhov_ful fulo signals 7 6.5 6 ns t ckcoh edge of clk1x to cascade output invalid (output hold) [30] t ckcoh_hit lho, bho signals 0.75 0.75 0.75 ns t ckcoh_ful fulo signals 1.2 1.2 1 ns t ckhovfe edge of clk1x to full signal valid (enhanced mode) 3.2 3 2.5 ns t ckhov_fne rising edge of clk1x to full signal valid (non- enhanced mode) 76.56ns t ckcohfe edge of clk1x to full invalid (enhanced mode) [30] 0.75 0.75 0.75 ns t ckcoh_fne rising edge of clk1x to full invalid (non- enhanced mode) [30] 1.2 1.2 1 ns t ckhdv rising edge of clk1x to dq valid [24] 3.5 3.0 2.5 ns t ckhdz rising edge of clk1x to dq high-z [28] 0.5 1.8 0.5 1.8 0.5 1.8 ns t ckhsv edge of clk1x to sram bus valid. [24] 3.5 3.0 2.5 ns t ckhshz edge of clk1x to sram bus high-z. [28] 0.5 1.8 0.5 1.8 0.5 1.8 ns t ckhslz edge of clk1x to sram bus low-z. [28] 1.9 1.9 1.9 ns t oh rising edge of clk1x to dq or sram bus invalid (output hold) 0.5 0.5 0.75 ns t rstl minimum low pulse width for rst_l 100 100 100 us [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 141 of 153 table 10-3. jtag timing parameters parameter description ayama 10000- 083 ayama 10000- 100 ayama 10000- 133 unit min. max. min. max. min. max. f jtag maximum jtag tap controller frequency 10 10 10 mhz t tcyc tck clock cycle time 100 100 100 ns t ih tck clock high time 40 40 40 ns t tl tck clock low time 40 40 40 ns t tmss tms set-up to tck clock rise 10 10 10 ns t tmsh tms hold after tck clock rise 10 10 10 ns t tdis tdi set-up to tck clock rise 10 10 10 ns t tdih tdi hold after tck clock rise 10 10 10 ns t tdov tck clock low to tdo valid 10 10 10 ns t tdox tck clock low to tdo invalid 10 10 10 ns [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 142 of 153 signal signal signal signal group 2 group 3 group 5 group 4 t icsch* t ihch signal group 1a: dq, cmd signal group 1b: cmdv signal group 2: lhi, bhi, fuli signal group 3: lho, bho, fulo, full (non-enhanced) signal group 4: sadr, ce_l, oe_l, we_l, ale_l, ssf, ssv signal group 5: dq, ack, eot, multi_hit, par, full (enhanced) t ckhov* t ckhov* t ckhdz t ckhdv, t ckhovfe t ckhshz t ckhslz t ckhsv clk1x signal group 1a t isch t ihch t isch t ichch* figure 10-2. ac timing wave forms with clk1x signal group 1b t ihch t isch signal group 4 t ckhshz t ckhslz t ckhsv (multisearch) t ckhsv t oh [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 143 of 153 10.3 ac test conditions and output loads the following test conditions are the equivale nt of the actual tester measurement condit ion. the effect of transmission line is removed from the results. 10.3.1 lvcmos 2.5v/1.8v table 10-4. 2.5v / 1.8v ac table for lvcmos test condition of ayama 10000 conditions results input pulse levels gnd to 2.5v / 1.8v input rise and fall times measured for 2.5v lvcmos at 0.25v and 2.25v 1.2 ns (see figure 10-3 ) input rise and fall times measured for 1.8v lvcmos at 0.18v and 1.98v 1.2 ns (see figure 10-3 ) input timing reference levels (2.5v / 1.8v) 1.25v / 0.9v output reference levels (2.5v / 1.8v) 1.25v / 0.9v figure 10-3. lvcmos i/o input waveform +2.5v / +1.8v 90% 10% gnd 90% 10% figure 10-4. test condition of 2.5v lvcmos i/o output load equivalent 50 ? d out 6pf v l = 1/2 * v ddq v ddq = 2.5v 479 ? 6 pf d out 523 ? figure 10-5. test condition of 2.5v high-z lvcmos i/o output load equivalent for high-z v ddq = 1.8v 470 ? 6 pf d out 470 ? figure 10-6. test condition of 1.8v high-z lvcmos i/o output load equivalent for high-z [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 144 of 153 10.3.2 hstl i/ii table 10-5. 1.5v ac table for hstl test condition of ayama 10000 conditions results input pulse levels 0.25 to 1.25v input rise and fall times measured at 20% and 80% of input pulse faster than 1 v/ns (see figure 10-7 ) input timing reference levels 0.75v output reference levels 0.75v figure 10-7. hstl i/ii i/o input waveform +1.25v 80% 20% 0.25v 80% 20% figure 10-8. test condition of hstl i i/o output load equivalent 50 ? d out 6pf v l = 1/2 * v ddq figure 10-9. test condition of hstl ii i/o output load equivalent 25 ? d out 6pf v l = 1/2 * v ddq v ddq = 1.5v 479 ? 6 pf d out 523 ? figure 10-10. test condition of hstli/ii i/o high-z output load equivalent for high-z [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 145 of 153 11.0 pin assignment and pinout diagram figure 11-1 shows the pinout diagram and table 11-1 lists the pins assignment for ayama 10000. af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a 1 nc vss rst _l vss full fulo[ 1] fuli [ 6 ] vddq_a fuli [ 2 ] fuli [ 0 ] bho[ 2 ] vddq_a bho[ 0 ] bhi [ 1] vddq_a lho[ 0 ] lhi [ 6 ] lhi [ 2 ] lhi [ 0 ] i d[ 3 ] i d[ 1] i d[ 0 ] t rst _l t ck t di nc 1 2 nc vss vddq_a eot ack asicsel fulo[0] fuli[5] fuli[3] vddq_a vss bho[1] m ulti _hi t bhi[2] bhi[0] lho[1] lhi[4] lhi[3] lhi[1] id[4] id[2] vddq_j tdo tms vss dq[71] 2 3 dq[ 6 8 ] dq[ 7 0 ] vdd vdd vdd vdd vdd nc fuli [ 4 ] fuli [ 1] vdd vdd vdd vdd vdd vdd lhi [ 5 ] vddq_a parerr_l vdd vdd vdd vdd vdd dq[ 6 9 ] vddq_a 3 4 dq[ 6 6 ] vddq_a vdd vss vss vss vss vss vss vss vdd vdd vdd vdd vdd vdd vss vss vss vss vss vss vss vdd dq[ 6 5 ] dq[ 6 7 ] 4 5 dq[ 6 2 ] dq[ 6 4 ] vdd vss vss vdd dq[ 6 1] dq[ 6 3 ] 5 6 vddq_a dq[ 6 0 ] vdd vss vss vdd dq[ 5 9 ] vddq_a 6 7 dq[ 5 6 ] dq[ 5 8 ] vdd vss vss vdd dq[ 5 5 ] dq[ 5 7 ] 7 8 dq[ 5 2 ] dq[ 5 4 ] hsvref0 vss vss hsvref1 vddq_a dq[ 5 3 ] 8 9 dq[ 4 8 ] dq[ 5 0 ] vddq_a vss vss dq[49] dq[47] dq[51] 9 10 vddq_a dq[ 4 4 ] dq[ 4 6 ] vss vs s v ddq_a dq[ 4 5 ] dq[ 4 3 ] 10 11 dq[ 4 0 ] dq[ 4 2 ] vdd vdd vss vss vss vss vss vss vdd vdd dq[ 3 9 ] dq[ 4 1] 11 12 dq[ 3 6 ] dq[ 3 8 ] vdd vdd vss vss vss vss vss vss vdd vdd vddq_a dq[ 3 7 ] 12 13 dq[ 3 4 ] vddq_a vdd vdd vss vss vss vss vss vss vdd vdd dq[ 3 3 ] dq[ 3 5 ] 13 14 dq[ 3 0 ] dq[ 3 2 ] vdd vdd vss vss vss vss vss vss vdd vdd dq[ 2 9 ] dq[ 3 1] 14 15 vddq_a dq[ 2 8 ] vdd vdd vss vss vss vss vss vss vdd vdd dq[ 2 7 ] vddq_a 15 16 dq[ 2 4 ] dq[ 2 6 ] vdd vdd vss vss vss vss vss vss vdd vdd dq[ 2 3 ] dq[ 2 5 ] 16 17 dq[ 2 2 ] vddq_a dq[ 2 0 ] vss v s s dq[ 19 ] v ddq_a dq[ 2 1] 17 18 dq[14] dq[18] dq[16] vss v s s dq[ 13 ] dq[ 15 ] d q[ 17 ] 18 19 vddq_a dq[ 12 ] par[ 0 ] vss vss par[ 1] dq[ 11] vddq_a 19 20 dq[ 8 ] dq[ 10 ] vdd vss vss vdd dq[ 7 ] dq[ 9 ] 20 21 dq[ 4 ] dq[ 6 ] vdd vss hi gh_spee d v dd v ddq_a dq[ 5 ] 21 22 dq[ 2 ] vddq_a vdd vss vss vdd dq[ 1] dq[ 3 ] 22 23 ssv dq[ 0 ] vdd vss vss vss vss vss vss vss_pll vdd vdd vdd vdd vdd vdd vss vss vss vss vss vss vss vdd vss vss 23 24 ssf vddq_a vdd vdd vdd vdd vdd sadr[ 2 4 ] ce_l oe_l vdd_pll vdd vdd vdd vdd vdd sadr[ 13 ] sadr[ 11] sadr[ 2 5 ] vdd vdd vdd vdd vdd cfg_l sram sel 24 25 cm d[ 10 ] vss cm d[ 8 ] cm d[ 6 ] cm d[ 5 ] cm d[ 3 ] cm d[ 1] cm dv vddq_s phs_l clk_m od e sadr[ 2 2 ] sadr[ 2 1] sadr[ 19 ] vddq_s sadr[ 15 ] vddq_s sadr[ 12 ] vddq_s sadr[ 8 ] sadr[ 6 ] sadr[ 5 ] sadr[ 3 ] sadr[ 1] vss gh_spee d 25 26 cm d[ 9 ] nc cm d[ 7 ] vdd_a cm d[ 4 ] cm d[ 2 ] cm d[ 0 ] ale_l we_l l k1x/ clk2 sadr[ 2 3 ] vddq_s sadr[ 2 0 ] sadr[ 18 ] sadr[ 17 ] sadr[ 16 ] sadr[ 14 ] sadr[ 10 ] sadr[ 9 ] sadr[ 7 ] vddq_s sadr[ 4 ] sadr[ 2 ] vddq_s sadr[ 0 ] nc 26 af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a figure 11-1. pinout diagram (top view) [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 146 of 153 table 11-1. pin assignment package ball number signal name signal type package ball number signal name signal type a1 nc no connect aa26 cmd[2] input a10 dq[43] i/o aa3 v dd 1.2v a11 dq[41] i/o aa4 v ss gnd a12 dq[37] i/o ab1 full output-t a13 dq[35] i/o ab2 ack output-t a14 dq[31] i/o ab23 v ss gnd a15 v ddq_asic 1.5v/1.8v/2.5v ab24 v dd 1.2v a16 dq[25] i/o ab25 cmd[5] input a17 dq[21] i/o ab26 cmd[4] input a18 dq[17] i/o ab3 v dd 1.2v a19 v ddq_asic 1.5v/1.8v/2.5v ab4 v ss gnd a2 dq[71] i/o ac1 v ss gnd a20 dq[09] i/o ac10 v ss gnd a21 dq[05] i/o ac11 v dd 1.2v a22 dq[03] i/o ac12 v dd 1.2v a23 v ss gnd ac13 v dd 1.2v a24 sramsel v ddq_sram /v ss ac14 v dd 1.2v a25 high_speed1 input ac15 v dd 1.2v a26 nc no connect ac16 v dd 1.2v a3 v ddq_asic 1.5v/1.8v/2.5v ac17 v ss gnd a4 dq[67] i/o ac18 v ss gnd a5 dq[63] i/o ac19 v ss gnd a6 v ddq_asic 1.5v/1.8v/2.5v ac2 eot output-t a7 dq[57] i/o ac20 v ss gnd a8 dq[53] i/o ac21 v ss gnd a9 dq[51] i/o ac22 v ss gnd aa1 fulo[1] output-t ac23 v ss gnd aa2 asicsel v ddq_asic /v ss ac24 v dd 1.2v aa23 v ss gnd ac25 cmd[6] input aa24 v dd 1.2 ac26 v ddq_asic 1.5v/1.8v/2.5v aa25 cmd[3] input ac3 v dd 1.2v ac4 v ss gnd ae10 dq[44] i/o ac5 v ss gnd ae11 dq[42] i/o ac6 v ss gnd ae12 dq[38] i/o ac7 v ss gnd ae13 v ddq_asic 1.5v/1.8v/2.5v ac8 v ss gnd ae14 dq[32] i/o ac9 v ss gnd ae15 dq[28] i/o ad1 rst_l input ae16 dq[26] i/o ad10 dq[46] i/o ae17 v ddq_asic 1.5v/1.8v/2.5v ad11 v dd 1.2v ae18 dq[18] i/o ad12 v dd 1.2v ae19 dq[12] i/o ad13 v dd 1.2v ae2 v ss gnd ad14 v dd 1.2v ae20 dq[10] i/o [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 147 of 153 ad15 v dd 1.2v ae21 dq[06] i/o ad16 v dd 1.2v ae22 v ddq_asic 1.5v/1.8v/2.5v ad17 dq[20] i/o ae23 dq[00] i/o ad18 dq[16] i/o ae24 v ddq_asic 1.5v/1.8v/2.5v ad19 par[0] i/o ae25 v ss gnd ad2 v ddq_asic 1.5v/1.8v/2.5v ae26 nc no connect ad20 v dd 1.2v ae3 dq[70] i/o ad21 v dd 1.2v ae4 v ddq_asic 1.5v/1.8v/2.5v ad22 v dd 1.2v ae5 dq[64] i/o ad23 v dd 1.2v ae6 dq[60] i/o ad24 v dd 1.2v ae7 dq[58] i/o ad25 cmd[8] input ae8 dq[54] i/o ad26 cmd[7] input ae9 dq[50] i/o ad3 v dd 1.2v af1 nc no connect ad4 v dd 1.2v af10 v ddq_asic 1.5v/1.8v2.5v ad5 v dd 1.2v af11 dq[40] i/o ad6 v dd 1.2v af12 dq[36] i/o ad7 v dd 1.2v af13 dq[34] i/o ad8 hsvref0 input af14 dq[30] i/o ad9 v ddq_asic 1.5v/1.8v/2.5v af15 v ddq_asic 1.5v/1.8v2.5v ae1 vss gnd af16 dq[24] i/o af17 dq[22] i/o b23 v ss gnd af18 dq[14] i/o b24 cfg_l input af19 v ddq_asic 1.5v/1.8v/2.5v b25 v ss gnd af2 nc no connect b26 sadr[0] output-t af20 dq[08] i/o b3 dq[69] i/o af21 dq[04] i/o b4 dq[65] i/o af22 dq[02] i/o b5 dq[61] i/o af23 ssv output-t b6 dq[59] i/o af24 ssf output-t b7 dq[55] i/o af25 cmd[10] input b8 v ddq_asic 1.5v/1.8v2.5v af26 cmd[9] input b9 dq[47] i/o af3 dq[68] i/o c1 tck input af4 dq[66] i/o c10 v ddq_asic 1.5v/1.8v2.5v af5 dq[62] i/o c11 v dd 1.2v af6 v ddq_asic 1.5v/1.8v/2.5v c12 v dd 1.2v af7 dq[56] i/o c13 v dd 1.2v af8 dq[52] i/o c14 v dd 1.2v af9 dq[48] i/o c15 v dd 1.2v b1 tdi input c16 v dd 1.2v b10 dq[45] i/o c17 dq[19] i/o b11 dq[39] i/o c18 dq[13] i/o b12 v ddq_asic 1.5v/1.8v/2.5v c19 par[1] i/o table 11-1. pin assignment (continued) package ball number signal name signal type package ball number signal name signal type [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 148 of 153 b13 dq[33] i/o c2 tms input b14 dq[29] i/o c20 v dd 1.2v b15 dq[27] i/o c21 v dd 1.2v b16 dq[23] i/o c22 v dd 1.2v b17 v ddq_asic 1.5v/1.8v/2.5v c23 v dd 1.2v b18 dq[15] i/o c24 v dd 1.2v b19 dq[11] i/o c25 sadr[1] output-t b2 v ss gnd c26 v ddq_sram 1.5v/1.8v/2.5v b20 dq[7] i/o c3 v dd 1.2v b21 v ddq_asic 1.5v/1.8v/2.5v c4 v dd 1.2v b22 dq[1] i/o c5 v dd 1.2v c6 v dd 1.2v e24 v dd 1.2v c7 v dd 1.2v e25 sadr[5] output-t c8 hsvref1 input e26 sadr[4] output-t c9 dq[49] i/o e3 v dd 1.2v d1 trst_l input e4 v ss gnd d10 v ss gnd f1 id[1] input d11 v dd 1.2v f2 id[2] input d12 v dd 1.2v f23 v ss gnd d13 v dd 1.2v f24 v dd 1.2v d14 v dd 1.2v f25 sadr[6] output-t d15 v dd 1.2v f26 v ddq_sram 1.5v/1.8v/2.5v d16 v dd 1.2v f3 v dd 1.2v d17 v ss gnd f4 v ss gnd d18 v ss gnd g1 id[3] input d19 v ss gnd g2 id[4] input d2 tdo output-t g23 v ss gnd d20 v ss gnd g24 v dd 1.2v d21 high_speed2 input g25 sadr[8] output-t d22 v ss gnd g26 sadr[7] output-t d23 v ss gnd g3 v dd 1.2v d24 v dd 1.2v g4 v ss gnd d25 sadr[3] output-t h1 lhi[0] input d26 sadr[2] output-t h2 lhi[1] input d3 v dd 1.2v h23 v ss gnd d4 v ss gnd h24 sadr[25] [31] output-t d5 v ss gnd h25 v ddq_sram 1.5v/1.8v/2.5v d6 v ss gnd h26 sadr[9] output-t d7 v ss gnd h3 parerr_l output-open drain d8 v ss gnd h4 v ss gnd d9 v ss gnd j1 lhi[2] input e1 id[0] input j2 lhi[3] input e2 v ddq_jtag 2.5v j23 v ss gnd table 11-1. pin assignment (continued) package ball number signal name signal type package ball number signal name signal type [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 149 of 153 e23 v ss gnd j24 sadr[11] output-t j25 sadr[12] output-t m2 bhi[0] input j26 sadr[10] output-t m23 v dd 1.2v j3 v ddq_asic 1.5v/1.8v/2.5v m24 v dd 1.2v j4 v ss gnd m25 v ddq_sram 1.5v/1.8v/2.5v k1 lhi[6] input m26 sadr[17] output-t k2 lhi[4] input m3 v dd 1.2v k23 v ss gnd m4 v dd 1.2v k24 sadr[13] output-t n1 bhi[1] input k25 v ddq_sram 1.5v/1.8v/2.5v n11 v ss gnd k26 sadr[14] output-t n12 v ss gnd k3 lhi[5] input n13 v ss gnd k4 v ss gnd n14 v ss gnd l1 lho[0] output-t n15 v ss gnd l11 v ss gnd n16 v ss gnd l12 v ss gnd n2 bhi[2] input l13 v ss gnd n23 v dd 1.2v l14 v ss gnd n24 v dd 1.2v l15 v ss gnd n25 sadr[19] output-t l16 v ss gnd n26 sadr[18] output-t l2 lho[1] output-t n3 v dd 1.2v l23 v dd 1.2v n4 v dd 1.2v l24 v dd 1.2v p1 bho[0] output-t l25 sadr[15] output-t p11 v ss gnd l26 sadr[16] output-t p12 v ss gnd l3 v dd 1.2v p13 v ss gnd l4 v dd 1.2v p14 v ss gnd m1 v ddq_asic 1.5v/1.8v/2.5v p15 v ss gnd m11 v ss gnd p16 v ss gnd m12 v ss gnd p2 multi_hit output-t m13 v ss gnd p23 v dd 1.2v m14 v ss gnd p24 v dd 1.2v m15 v ss gnd p25 sadr[21] output-t m16 v ss gnd p26 sadr[20] output-t p3 v dd 1.2v u24 oe_l output-t p4 v dd 1.2v u25 phs_l input r1 v ddq_asic 1.5v/1.8v/2.5v u26 clk1x/clk2x input r11 v ss gnd u3 fuli[1] input r12 v ss gnd u4 v ss gnd r13 v ss gnd v1 fuli[2] input r14 v ss gnd v2 fuli[3] input r15 v ss gnd v23 v ss gnd r16 v ss gnd v24 ce_l output-t table 11-1. pin assignment (continued) package ball number signal name signal type package ball number signal name signal type [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 150 of 153 notes: 31. no-connect in cynse10256 and CYNSE10128. 32. no-connect in cynse10256. r2 bho[1] output-t v25 v ddq_sram 1.5v/1.8v/2.5v r23 v dd 1.2v v26 we_l output-t r24 v dd 1.2v v3 fuli[4] input r25 sadr[22] output-t v4 v ss gnd r26 v ddq_sram 1.5v/1.8v/2.5v w1 v ddq_asic 1.5v/1.8v/2.5v r3 v dd 1.2v w2 fuli[5] input r4 v dd 1.2v w23 v ss gnd t1 bho[2] output -t w24 sadr[24] [32] output-t t11 v ss gnd w25 cmdv input t12 v ss gnd w26 ale_l output-t t13 v ss gnd w3 nc no connect t14 v ss gnd w4 v ss gnd t15 v ss gnd y1 fuli[6] input t16 v ss gnd y2 fulo[0] output-t t2 v ss gnd y23 v ss gnd t23 v dd 1.2v y24 v dd 1.2v t24 v dd_pll 1.2v y25 cmd[1] input t25 clk_mode input y26 cmd[0] input t26 sadr[23] output-t y3 v dd 1.2v t3 v dd 1.2v y4 v ss gnd t4 v dd 1.2v u1 fuli[0] input u2 v ddq_asic 1.5v/1.8v/2.5v u23 v ss_pll gnd table 11-1. pin assignment (continued) package ball number signal name signal type package ball number signal name signal type [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 151 of 153 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems wh ere a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. 12.0 package diagrams 13.0 ordering information table 13-1 provides ordering information. ayama, mini-key, multisearch, and soft priority are trademarks of cypress semi conductor. all product and company names mentioned in this document may be the tr ademarks of their respective holders. table 13-1. ordering information part number description i/o voltage max. freq. temp. range cynse10512?83fgc/i 83-msps 512k x 36-b it entries nse 1.5v/1.8v/2.5v 83 mhz comm/ind cynse10512?100fgc 100-msps 512k x 36-bit entries nse 1.5v/1.8v/2.5v 100 mhz comm cynse10512?133fgc 133-msps 512k x 36-bit entries nse 1.5v/1.8v/2.5v 133 mhz comm cynse10256?83fgc/i 83-msps 256k x 36-b it entries nse 1.5v/1.8v/2.5v 83 mhz comm/ind cynse10256?100fgc 100-msps 256k x 36-bit entries nse 1.5v/1.8v/2.5v 100 mhz comm cynse10256?133fgc 133-msps 256k x 36-bit entries nse 1.5v/1.8v/2.5v 133 mhz comm CYNSE10128?083fgc/i 83-msps 128k x 36-b it entries nse 1.5v/1.8v/2.5v 83 mhz comm/ind CYNSE10128?100fgc 100-msps 128k x 36-bit entries nse 1.5v/1.8v/2.5v 100 mhz comm CYNSE10128?133fgc 133-msps 128k x 36-bit entries nse 1.5v/1.8v/2.5v 133 mhz comm ac ae ad af aa w y v ab g m n r u p t j l h k c e b f d a 17 25 26 21 22 24 23 19 18 20 2 10 14 16 15 12 11 13 6 7 8 9 4 3 51 9 7 5 3 125 23 21 19 17 15 13 11 8 6 4 2162426 20 22 18 12 14 10 ad ab af ac ae u v y w aa p t r n c h k m j l d f e g b a seating plane a b 0.15(4x) 31.75 15.875 1.27 35.000.10 35.000.10 31.75 1.27 15.875 ?0.750.05(388x) ?0.30 m c a b ?0.15 m c a1 corner a1 corner // 0.25 c 0.20 c c 3.32 max 2.440.18 0.600.05 1.10 reference jedec ms-034 51-85169-*b 388-ball hfc-bga fg388a [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 152 of 153 document history page document title: cynse10512/cynse10256/CYNSE10128 ayama 10000 network search engine document number: 38-02069 rev. ecn no. issue date orig. of change description of change ** 119954 01/16/03 bgt new data sheet *a 123910 02/13/03 khs for itl added the following information: 32 clk2x cycles wait after a write to command register enhanced mode block configuration (in bmr) prior to entries initialization blocks initialization prior to accessing the blocks clarification on static signals voltage level external pull-up resistor requirement for parerr_l signal *b 126318 05/09/03 khs section 5.1.2.3: parerr changed to active-low parerr_l updated the timing of parerr_l signal validity section 5.3.14: updated srr?s priority fiel d definition for when search operation resulted in a miss section 5.12: modified the statement on how to control trst_l section 6.2: fixed learn command b-cycle bi t[7] on enhanced mode for x288/x576 from ?x? to ?0? figure 6.3: updated parerr_l signal valid per section 5.1.2.3 update figure 6-6 and 6-8: ssv to refl ect idle cycles on 288-bit searches section 6.6: note on mismatched entry width learn operation figure 6-57, 6-58 and 6-59: added ale_l signal section 11 and section 12: added package orientations figure 11-1 and table 11-1: pin aa24 changed from vddq_sram to vdd *c 129255 10/08/03 khs table 4-1: added cfg_l signa l and description (signal is bonded out to b24) table 4-1: corrected the dq direction to i/o section 4.0, note 4: updated parerr_l pull-up resistance recommendation table 4-1: corrected par[1:0] direction to i/o table 4-1: updated high_speed 1 and high_speed2 description table 4-1: corrected polarity mode of fuli[6:0] and fulo[1:0] section 5.1.2.3: updated description of parity feature figure 5-4; figure 5-5: added timing diagrams of dq and core parity error section 5.1.2.4: corrected description of clk2x section 5.4.1: clarify cmpr registers width section 5.4.2: clarify gmr registers width table 5-5: renamed register name from stat us to successful and updated index field figure 5-11, table 5-6: removed read bit. it is now reserved. table 5-8 and 5-9: replaced adr with index table 5-12: updated hardware register fields table 5-13: update adr description table 5-17: corrected minikey3 range table 5-20: clarify f3 field description table 5-26: corrected indirect description section 5.10.1: corrected typo on 64k x 288 section 6.2.1-3: replaced sadr with eadr, added note section 6.3.2: added to description of burst read table 6-3: corrected typos section 6.4.2: added to description of burst write section 6.4.3: added to description of parallel write figure 6-15: rewording on one of the notes section 6-6: added explanation of blind learn and learn suppression. figure 6-56/57: added timing diagrams for x72 and x288 learn section 6.8: added section on timing sequences for back-to-back operations section 6.9: added section on full signal: description and timing diagram section 9.0: added maximum ratings data and rearranged the parameters table 10-1: updated the descriptions of the timing parameters and notes figure 10-1: added phs_l and clarify boundaries of parameters figure 10-2: clarify boundaries of parameters table 11-1: added cfg_l to pin list and removed dq[72] *d 205841 xbm minor change: upload mpn to external website [+] feedback [+] feedback
confidential preliminary cynse10512 cynse10256 CYNSE10128 document #: 38-02069 rev. *f page 153 of 153 *e 212292 see ecn khs p10: 576-bit configuration is supported in enhanced mode only p15-p17, table 4-1: general si gnal description clarification p27, figure 5-9: added addresses value of the gmr registers p28, table5-4: gval is valid only in enhanced mode p29, table 5-5: clarified operati ons that are affected by hlat p33, table 5-11: corrected locations of the io interfaces control bits and drive strengths p41, section 5.6: clarified phase cycles of clk2x p42, figure 5-27, 5-28, 5-29: added cycl e a and cycle b references to diagrams p43, table 5-24: clarified operating speed clock references p48, section 5.11: clarified description of indirect read p50, section 6.1: clarified cycle a, cycle b description s relative to command encoding p53, figure 6-2: changed eot low cycle time p95, section 6.5.8: removed redundant note on multisearch p113-114, section 6.6: clarified learn description p115, figure 6-57: corrected timing di agram to add a cycle between commands p116, figure 6-58: added 576-bit learn dq timing diagram p117, figure 6-59: added 576-bit learn cmpr timing diagram p121-p133, various: corrected sr am operation timing diagram p133, section 6-8: added exam ples of back-to-back operations p133, note 16: clarified note description p133, note 19: new note on learn operation p136, section 9.0: modified storage temp erature range and latch-up current rating p136-p137, table 9-1 part 1: expanded st andby and operating current parameters p137, table 9-1 part 2: added load capacitance for cmd bus p137, table 9-2: added commercial and industrial ambient temperature ranges p138, table 10-1: updated the following pa rameters: fclock, tihch, tichch, tckhdv, tckhsv, tckhdz, tckhshz, tisch p139, figure 10-1: added full, par, multi_hit p140, table 10-2: updated the following pa rameters: fclock, tihch, tichch, tckhdv, tckhsv, tckhdz, tckhshz, tisch p141, figure 10-2: added full, par, multi_hit p142, figure 10-4, 10-5, 10-6: updated diagrams to best repr esent actual test condition p143, figure 10-8, 10-9, 10-10: updated diagrams to best repr esent actual test condition p149, table 11-1: added notes to identify pi ns that are not valid for smaller densities other: removed all references to cascade performance. *f 239580 see ecn dcu p134, figure 6-77: added diagram for non- enhanced mode full, corrected tlsz error p140, figure 10-1: added signal group for mu ltisearch operation timing, clarified cycle relationship p138, table 10-1: expanded clk2x ac timing parameters table for cascade signals, added minimum pulse width for rst_l p139, table 10-2: expanded clk1x ac timing parameters table for cascade signals, added minimum pulse width for rst_l p142, figure 10-2: added signal group for mu ltisearch operation timing, clarified cycle relationship, removed reference to internal clock p49, figure 5-35: clarified power-up sequence figure and description p15, table 4-1: clarified cycle timing for device activation after rst_l p141, table 10-3: added jtag ac timing table p137, table 9-1: removed table cells and replaced with a note p55, section 6.4.3: clarifi ed parallel write description document title: cynse10512/cynse10256/CYNSE10128 ayama 10000 network search engine document number: 38-02069 rev. ecn no. issue date orig. of change description of change [+] feedback [+] feedback

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